in verilog 19. We like to design a 32-bit, 4-to1 mux; i.e. a circuit that select
ID: 3349061 • Letter: I
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in verilog
19. We like to design a 32-bit, 4-to1 mux; i.e. a circuit that selects amongst four 32-bit inputs, ao, al, a2, a3, based on a 2-bit control signal c. For example, if c is 2 (i.e 10 in binary) then the circuit's output z must be a2. Call it yMux4to1.v. 20. Rather than reinventing the wheel, we can benefit from our existing 32-bit, 2-to-1 yMux. This circuit claims to have the desired functionality module yMux4to1 (z, a0,al, a2, a3, c) parameter SIZE 2; output [SIZE-1:0 zi input [SIZE-1:01 a0, al, a2, a3 input 1:01 c wire [SIZE-1:0 zLo, zHi; yMux yMux yMux #(SIZE) #(SIZE) #(SIZE) lo(zLo, ao, al, c [0]); hi {zHi , a2, a3, c [0]); final {z, zLo, Eil , c [1]); endmodule 21. Draw the circuit's diagram and use it to argue that this implementation does indeed have the correct functionality of a 4-to-1 mux 22. Create LabL4.v so it instantiates and tests yMux4to1. Use random testing to create various test cases and an oracle to verify the functionality. Does the four-way mux behave as expected?Explanation / Answer
19)
////////////VERILOG CODE for 32 bit ax1 MUX/////////////
module yMux4to1 (a0,a1,a2,a3,c,z);
input [31:0] a0,a1,a2,a3; //inputs of size 32 bit
input [1:0] c; //selection line for multiplexer
output [31:0] z; //output which gives any one of 4 inputs
reg[31:0] z;
always @ (a0 or a1 or a2 or a3 or c) //any change in these inputs cause immediate change in the out put
begin
case (c)
2'b00 : z <= a0; //output is a0 if c=0
2'b01 : z <= a1; //output is a1 if c=1
2'b10 : z <= a2; //output is a2 if c=2
2'b11 : z <= a3; //output is a3 if c=3
endcase
end
endmodule
//(If you have any query leave a comment, Thank you)
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