I RAM Design 1. Requirement Write VHDL code for a RAM that has 16 locations each
ID: 3348676 • Letter: I
Question
I RAM Design 1. Requirement Write VHDL code for a RAM that has 16 locations each 32 bits wide. There wll be a Chip Select (CS input that activates the chip. Another input to the circuit is an R/W which determines if the operation is read or a write to the chip. The address input to the chip is a vector. The input and output would also be vector(s) that should send and receive the data, depending on the address input to the chip. Clk CS Address R/W Data In Data Out RAM 16x32 bits The interface can be declared as below: entity RAM 32B?ts is port Clk:instd logic cs:instd logic; R W:instd logic Address:instd logic vector (Sdownto) Data In:instd logic vector (31 downtoo) : Data Out:outstd logic vector (31 downto) 2. Pre-lab Study and analyze the working of a RAM 3. Lab Write the VHDL code for this RAM design (recommend using conversion functions located in numeric sta library for index conversion for array) Simulate using Xilinx Vivado simulator VHDL test bench with enough testcasesExplanation / Answer
VHDL Code for RAM Design:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity RAM_32Bits is
port (
Clk: in std_logic;
CS: in std_logic;
RW: in std_logic;
Address: in std_logic_vector(3 downto 0);
Data_In: in std_logic_vector(31downto 0);
Data_Out: out std_logic_vector(31downto 0);
)
end entity RAM_32Bits;
architecture RAM_32 of RAM_32Bits is
// Declare Memory Array
type RAM is array (3 downto 0) of std_logic_vector(31 downto 0);
signal mem_array: ram;
// Signal Declaration
signal read_addr: std_logic_vector (3 downto 0);
begin
process (Clk)
begin
if (Clk’event and Clk=’1’) then
if (CS=’1’ and RW=’1’) then
ram(conv_integer(Address)) <= Data_In;
endif;
if (CS=’1’ and RW=’0’) then
read_addr <= Address;
endif;
else
read_addr <= read_addr;
endif;
endprocess
Data_Out <= ram[conv_integer(read_addr)];
end architecture RAM_32;
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