There is a 2GHz processor with two levels of cache. L1 cache is 2KiB with a bloc
ID: 2991188 • Letter: T
Question
There is a 2GHz processor with two levels of cache. L1 cache is 2KiB with a block size of 4 words. L2 cache is 4KiB with a block size of 2 words. Both L1 and L2 are direct-mapped caches. The operating system manages a page table with a 1KiB page size and a fully-associative TLB with 4 entries that are each one page in size. New entries to the page table should increment the highest used physical page.
The access time for L1 and L2 are 2 clock cycles and 13 clock cycles, respectively. The TLB requires 31 clock cycles to access and the page table takes 48 clock cycles to access. Physical memory (main memory) takes 200 clock cycles to access, and accessing disk will cost 100,000 clock cycles.
The initial state of the cache, page table, and TLB are as follows. All addresses are 32 bits.
L1 Cache
Valid
Tag
Index
1
8
1
1
0
4
1
9
13
0
1
3
1
0
64
1
0
86
L2 Cache
Valid
Tag
Index
1
0
0
1
0
255
1
9
13
1
1
3
0
1
22
1
2
189
TLB
Valid
Tag
Physical
Page
Last Access
1
0
1
1
5
10
1
1
0
1
8
6
Page Table
Entry
Valid
Physical Page or Disk
0
1
1
1
1
0
2
1
4
3
0
Disk
4
1
12
5
1
10
6
0
Disk
7
0
Disk
8
1
6
9
1
0
10
0
Disk
11
1
5
Fill in the missing information from the following tables regarding the bit fields in each level of cache.
L1 cache bits
Bit Field Description
Number of Bits
Reason
Byte offset bits
Word offset bits
Index bits
Tag bits
L2 cache bits
Bit Field Description
Number of Bits
Reason
Byte offset bits
Word offset bits
Index bits
Tag bits
What is the total time the system will take to access the following virtual byte addresses? Fill in the table on the next page as well as the sentence following the table.
0, 355, 2000, 7168, 11752, 116386
Virtual Byte Address
Virtual Page
Page Offset
TLB Tag
TLB Index
TLB Hit/ Miss
Time for TLB (cycles)
PT Hit/Miss
Time for PT (cycles)
Physical Page
0
--
355
--
2000
--
7168
--
11752
--
116386
--
Physical Byte Address
Physical Word Address
L1 Block Address
L1 Tag
L1 Index
L1 Hit/ Miss
Time for L1 (cycles)
L2 Block Address
L2 Tag
L2 Index
L2 Hit/ Miss
Time for L2 (cycles)
Total Time (cycles)
The total time to access the given virtual addresses is (fill in the blanks):
____________ clock cycles, or
____________ microseconds.
Here is an Example Problem!!!!!!!!!!!
Combined Virtual Memory and Cache
Problem 2
There is a 4GHz processor with two levels of cache. L1 cache is 4KiB and is direct-mapped with a block size of 8 words. L2 cache is 16KiB and is 4-way set associative with a block size of 4 words. The access time for L1 and L2 are 1 clock cycle and 5 clock cycles, respectively. It takes 100 clock cycles to access physical memory which has 2GiB of addressable space. The operating system manages a page table with a 2KiB page size and a fully-associative TLB with 8 entries that are each one page in size. New entries to the page table should use the next available physical page, and it takes 100,000 clock cycles to access disk. All addresses are 32 bits. The initial state of the cache, page table, and TLB are as follows.
Initial Conclusions
L1 cache bits (access time = 1 clock cycle)
Byte offset bits
2
Word offset bits
3
(8 words per block, 23 = 8)
Index bits
7
(4KiB / 4 bytes per word / 8 words per block = 128 blocks, 27 = 128)
Tag bits
20
(32
L1 Cache
Valid
Tag
Index
1
8
1
1
0
4
1
9
13
0
1
3
1
0
64
1
0
86
Explanation / Answer
Virtual Byte Address
Virtual Page
Page Offset
TLB Tag
TLB Index
TLB Hit/ Miss
Time for TLB (cycles)
PT Hit/Miss
Time for PT (cycles)
Physical Page
0
0
0
0
--
H
15
--
--
1
2040
0
2040
0
--
H
15
--
--
1
2048
1
0
0
--
H
15
--
--
1
8192
4
0
0
--
H
15
--
--
1
16480
8
96
1
--
M
30
H
40
0
132488
64
1416
8
--
M
30
M
100,080
16
Virtual Byte Address / 2KiB
Virtual Byte Address % 2KiB
Virtual Page / 8 TLB entries
N/A (fully associative)
TLB access time. If missed, the TLB will be accessed twice.
PT access time. If missed, the PT will be accessed twice, plus a disk access.
From TLB lookup or PT lookup
Physical Byte Address
Physical Word Address
L1 Block Address
L1 Tag
L1 Index
L1 Hit/ Miss
Time for L1 (cycles)
L2 Block Address
L2 Tag
L2 Index (LRU replacement not shown)
L2 Hit/ Miss
Time for L2 (cycles)
Total Time (cycles)
2048
512
64
0
64
H
1
--
--
--
--
--
16
4088
1022
127
0
127
M
2
255
0
255
H
5
22
2048
512
64
0
64
H
1
--
--
--
--
--
16
2048
512
64
0
64
H
1
--
--
--
--
--
16
96
24
3
0
3
M
2
6
0
6
M
110
182
34184
8546
1068
8
44
M
2
2136
8
88
M
110
100,222
(2KiB * Physical Page) + (Page Offset)
Byte Address / 4 bytes per word
Word Address / 8 words per block
L1 Block Address / 128 indexes in L1
L1 Block Address % 128 indexes in L1
L1 access time. If missed, L1 will be accessed twice.
Word Address / 4 words per block
L2 Block Address / 256 indexes in L2
L2 Block Address % 256 indexes in L2
(can go in any of the 4
Virtual Byte Address
Virtual Page
Page Offset
TLB Tag
TLB Index
TLB Hit/ Miss
Time for TLB (cycles)
PT Hit/Miss
Time for PT (cycles)
Physical Page
0
0
0
0
--
H
15
--
--
1
2040
0
2040
0
--
H
15
--
--
1
2048
1
0
0
--
H
15
--
--
1
8192
4
0
0
--
H
15
--
--
1
16480
8
96
1
--
M
30
H
40
0
132488
64
1416
8
--
M
30
M
100,080
16
Virtual Byte Address / 2KiB
Virtual Byte Address % 2KiB
Virtual Page / 8 TLB entries
N/A (fully associative)
TLB access time. If missed, the TLB will be accessed twice.
PT access time. If missed, the PT will be accessed twice, plus a disk access.
From TLB lookup or PT lookup
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