1. Draw a circuit diagram for a sign extension unit that would extend a two\'s c

Question

1. Draw a circuit diagram for a sign extension unit that would extend a two's complement
number from 4 to 8 bits.

2. Consider an 8x8 multiplier similar to the 4x4 one in Figure 5.18c. Assume that each AND gate
has a delay of A and each adder has a delay of B. What is the overall delay of this multiplier?

3. a. Represent 3.75 in fixed point form with 4 bits for the integer portion and 4 bits for the
fractional point.
b. Represent -1.25 in the same form.
c. Now add 3.75 with -1.25 in the fixed point form.

Explanation / Answer

1.

http://web.doe.carleton.ca/~jknight/97.267/2607_11W/AdderLab2M_11.pdf

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