OBJECTIVES: Design and simulate a 4-bit Synchronous Up-Down Counter in Altera Ma
ID: 2990856 • Letter: O
Question
OBJECTIVES:
Design and simulate a 4-bit Synchronous Up-Down Counter in Altera Max Plus II.
DESCRIPTION:
Students will work with Altera Max+Plus II graphic design tool and simulator that was used on lab 1. The project covers design and simulation of sequential circuits.
Theory of operation: Explain how your circuit works, but do not give implementation details. This should be an expanded version of the introduction. That is to give a high level description of what your circuits do and how they do it. For example, you could explain any algorithms you implemented, any conditions or restrictions the user must observe to use the circuits, and the high level structure of your circuits at the block diagram level.
Design details: This subsection is where you can go into the details of your design. It should contain any logical expressions you use, any Karnaughmaps or algebraic simplifications you performed, and any tables or state diagrams for sequential circuits. It should explain design techniques if they are not self-explanatory. It should refer to the detailed documentation (such as schematic diagrams) explicitly. This section should also contain a description of any unusual problems you had and how you solved them.
Schematic Diagrams. Make sure all input and output connectors are labeled with the proper signal name. Add labels for any interior signals that appear in the written description of the circuit, especially those that appear in logical expressions.
The waveform resulting from the time simulation. Do as many simulations you consider that show the functionality. of the circuit. You should set the waveform in the same order of variables that you provide in the truth tables.
Analysis, including comments and conclusions.
Explanation / Answer
ibrary ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity up_down_counter is
port(clk, rst_a, mode : in std_logic; --mode=1 up counting, mode=0 down counting
q : out std_logic_vector(3 downto 0));
end up_down_counter;
architecture archi of up_down_counter is
signal tmp: std_logic_vector(3 downto 0);
begin
process (clk, rst_a)
begin
if (rst_a='1') then
tmp <= "0000";
elsif (clk'event and clk='1') then
if (mode='1') then
tmp <= tmp + 1;
else
tmp <= tmp - 1;
end if;
end if;
end process;
q <= tmp;
end archi;
Test Bench
library ieee;
use ieee.std_logic_1164.all;
entity up_down_counter_tst is
end up_down_counter_tst;
architecture beh of up_down_counter_tst is
component up_down_counter
port(clk, rst_a,mode : in std_logic;
q : out std_logic_vector(3 downto 0));
end component;
signal clk_s,rst_a_s,mode_s : std_logic;
signal q_s : std_logic_vector(3 downto 0);
begin -- beh
u1 : up_down_counter port map (
clk => clk_s,
rst_a => rst_a_s,
mode => mode_s,
q => q_s);
clockk: process
begin -- process clockk
clk_s <= '1';
wait for 55 ns;
clk_s <= '0';
wait for 55 ns;
end process clockk;
tst: process
begin -- process tst
rst_a_s <= '1';
wait for 100 ns;
rst_a_s <= '0';
mode_s <= '1';
wait for 100 ns;
rst_a_s <= '0';
mode_s <= '1';
wait for 100 ns;
rst_a_s <= '0';
mode_s <= '0';
wait for 100 ns;
rst_a_s <= '0';
mode_s <= '0';
wait for 100 ns;
rst_a_s <= '0';
mode_s <= '1';
wait for 100 ns;
rst_a_s <= '0';
mode_s <= '0';
wait for 100 ns;
rst_a_s <= '0';
mode_s <= '0';
wait for 100 ns;
rst_a_s <= '0';
mode_s <= '1';
wait for 100 ns;
end process tst;
end beh;
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