Multisim Counters (Simple) Dont write the report just explain how you did it and
ID: 2988449 • Letter: M
Question
Multisim Counters (Simple) Dont write the report just explain how you did it and screenshot it at stages etc.
A gaming machine company is developing a new machine. In order to control certain sequences I of actions, TWO counters are required with the following specifications :- ? A decade (0 to 9) counter which does not reach a count of 10 before resetting. ? A counter with sequence 1, 3, 5, 7, 9, 11, 13. This counter must also be constructed such that, if at start up, any unwanted state is entered, then it will go to state 1 directly. a) For both counters, design the circuit and then use a computer simulation program to prove their operation. Document all of the above stages and include a floppy disk showing a working simulation of both designs. d) Use the simulator to test both circuits. ?.) Write a full report on the above detailing all stages of design techniques. This should be :xtensively illustrated with relevant diagrams, pictures, tables and charts whilst keeping text o a minimum. our task should be broken down into the following :- ? design the circuit, showing & explaining all formulae, calculations, relevant theory and design concepts. ? Simulate the circuit using a suitable computer package. You should obtain screen-print to show that you have fully tested this simulation, and that it functions properly and meets the design specification.Explanation / Answer
module EvenOddCounter_FSM(clk, rst, cen, dir, count);
input clk, rst, cen, dir;
output [3:0] count; // this is how you declare a 4 bit signal initial Verilog
reg [3:0] count;
// parameter used to define states
// Define the remaining states for your FSM here
parameter S_0 = 4'b0000,
S_1 = 4'b0001,
// state registers for current state and next state
reg [3:0] currentstate;
reg [3:0] nextstate;
// state register procedure with asynchronous reset
always @(posedge rst or posedge clk)
begin
if (rst==1) // initial state
currentstate <= S_0;
else
currentstate <= nextstate;
end
// combinational logic procedure for FSM control logic
always @(currentstate or cen or dir)
begin
case (currentstate)
S_0: begin
// complete logic for state S_0
end
S_1: begin
// complete logic for remaining states
end
endmodule
// state register component with asynchronous reset
module stateregsiter(clk, rst, nextstate, currentstate);
input clk, rst;
input [3:0] nextstate;
output [3:0] currentstate;
reg [3:0] currentstate;
always @(posedge rst or posedge clk)
begin
// your code goes here
end
endmodule
// combinational logic component for FSM control logic
module fsmcontrol(cen, dir, currentstate, nextstate, count);
input cen, dir;
input [3:0] currentstate;
output [3:0] nextstate;
output [3:0] count;
reg [3:0] nextstate;
reg [3:0] count;
always @(currentstate or cen or dir)
begin
// your code goes here
end
endmodule
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