2. Create the sevenSegDecoder.v hd file a. Under \"Flow Navigator\" click \"Add
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2. Create the sevenSegDecoder.v hd file a. Under "Flow Navigator" click "Add sources." b. Select "Create or add design sources." c. Create sevenSegDecoder.vhd and then click "Finish. wide (3 downto 0) bits wide (0 to 6) (we won't be using the decimal d. Create an input vector named "sw" which is 4 bits e. Create an output vector named "seg" which is 7 point) f. Create an input named "negative" 3. In your VHDL source file sevenSegDecoder.vhd, edit it to implement the encoder you designed above .A when/else, if/else, or case statement might be helpful, you do not need to use kmaps and find each output (unless you desire the practice and headache) By looking at the Basys3's reference manual section on basic input/output (I/O), the 7 segment displays are ACTIVE LOW, meaning to turn an LED ON in our seven segment display, you need to write a 0 to it. So that means the logic is exactly inversed from our truth table. Here's the reference manual to see the explanation (include an explanation of this for your report) https://reference.digilentinc.com/basys3/refmanu al#basic ioExplanation / Answer
2. seven segment decoder:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ssd is
port (
clk : in std_logic;
sw : in std_logic_vector(3 downto 0); -- 4 bit switches input
seg : out std_logic_vector(0 to 6) -- 7 bit decoded output.
);
end ssd;
architecture Behavioral of ssd is
begin
process (clk,sw)
BEGIN
if (clk'event and clk='1') then
case sw is
when "0000"=> seg <="0000001"; -- '0'
when "0001"=> seg <="1001111"; -- '1'
when "0010"=> seg <="0010010"; -- '2'
when "0011"=> seg <="0000110"; -- '3'
when "0100"=> seg <="1001100"; -- '4'
when "0101"=> seg <="0100100"; -- '5'
when "0110"=> seg <="0100000"; -- '6'
when "0111"=> seg <="0001111"; -- '7'
when "1000"=> seg <="0000000"; -- '8'
when "1001"=> seg <="0000100"; -- '9' // nothing is displayed when a number more than 9 is given as input.
when others=> segment7 <="1111111";
end case;
end if;
end process;
end Behavioral;
3. implementation of encoder using decoder:
library ieee;
use ieee.std_logic_1164.all;
entity priority_encoder is
port (sw: in std_logic_vector(7 downto 1);
seg : out std_logic_vector(2 downto 0) );
end priority_encoder;
architecture a of priority_encoder is
begin
process(inp)
begin
if (sw(7)='1') then seg<="111";
elsif (sw(6)='1') then seg<="110";
elsif (sw(5)='1') then seg<="101";
elsif (sw(4)='1') then seg<="100";
elsif (sw(3)='1') then seg<="011";
elsif (sw(2)='1') then seg<="010";
elsif (sw(1)='1') then seg<="001";
else seg<="000";
end if;
end process;
end a;
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