& Locaions Contact Problem 2 Wirite a Verlog module for an SR latch named SR lat

Question

& Locaions Contact Problem 2 Wirite a Verlog module for an SR latch named SR latch You should use a Boolean expression for full credit. This means you have to deduce the Boolean experession for an SR latch from this table if you doa't remember it. The mputs shoveld be S and R, the outputs should be Q and Qn (the compliment of Q) For full credit use theminimum required and use indestion to organize each block Your solution should be efficient, and succinct Use Verilog not System Verilog Q" 1 1 illegal ave A

Explanation / Answer

SR FlipFlop Using Case Statement Verilog Code
Verilog Code
module SR_FlipFlop(
input J,
input K,
input clk,
output Q,
output Qbar
);
reg Q,Qbar;
always@(posedge clk)
begin
case({J,K})
2’b0_0:Q<=Q;
2’b0_1:Q<=1’b0;
2’b1_0:Q<=1’b1;
2’b1_1:Q<=1’bz;
endcase
end

endmodule

Test Bench
module SRflipflopTB;
// Inputs
reg J;
reg K;
reg clk;

// Outputs
wire Q;
wire Qbar;

// Instantiate the Unit Under Test (UUT)
SR_FlipFlop uut (
.J(J),
.K(K),
.clk(clk),
.Q(Q),
.Qbar(Qbar)
);
initial clk = 0;
always #10 clk = ~clk;
initial begin
// Initialize Inputs
J = 0;
K = 0;
clk = 0;

// Wait 100 ns for global reset to finish
#100;
J=0;
K=1;
  
#100
J=1;
K=0;
  
#100
J=1;
K=1;
  
// Add stimulus here

end
  
endmodule

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