3. (5 pts) PLL XTAL 0x10 10.0 MHz 12.0 MHz Ox l 0x12 Ox13 0x14 0x15 0x16 Reserve

Question

3. (5 pts) PLL XTAL 0x10 10.0 MHz 12.0 MHz Ox l 0x12 Ox13 0x14 0x15 0x16 Reserved 3.579545 MHz .6864 MHz 4 MHz .096 MHz 4.9152 MHz 5 MHz 5.12 MHz 13.56 MHz 14.31818 MHz 16.0 MHz 16.384 MHz 18.0 MHz 20.0 MHz 24.0 MHz 25.0 MHaz 0x4 0x6 Ox7 0x8 0x9 0x19 OxB 0xC OxD 0xE 6.144 MHz 7.3728 MHz 8 MHz 8.192 MHz Ox IB 0x1C OxID OxIE Table 4 XTAL values (5pts) A design requires using 24.0 MHz crystal. Fill in blank for step 2 only void PLL Init(void) /1 0) Use RCC2 SYSCTL_RCC2 R 0x80000000; 1 USERCC2 // 1) bypass PLL while initializing SYSCTL RCC2 R I= 0x00000800; // BYPASS2, PLL bypass /1 2) select the crystal value and oscillator source // clear XTAL field, bits 10-6 //configure for 16 MHz erystal SYSCTI RCC2 R 0x00000070 configure for sain oscillator source // 3) activate PLL by clearing PWRDN SYSCTL RCC2 R & ~0x00002000; // 4) set the desired systen divider I- 0x40000000; 1/ use 400 MHz PLL // clear systen clock divider SYSCTL RCC2R // configure for 80 MHz clock // 5) wait for the PLL to lock by polling PLLLRIS // ait for PLLRIS bit whilet (SYSCTL RIS R&0x00000040) 0) / 6) enable use of PLL by clearing BYPASS SYSCTL RCC2 R &= ~0x00000800;

Explanation / Answer

XTAL 0x15 provides Frequency =16MHz

SYSCTL_RCC_R =0x00000030

SYSCTL_RCC_R= 0x00000570

Related Questions

Navigate

• Browse (All)
• Browse 3
• Subjects

---

---

Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.