3. FIG. 2 gives the state diagram of a synchronous sequential circuit having a Y
ID: 2292195 • Letter: 3
Question
3.
FIG. 2 gives the state diagram of a synchronous sequential circuit having a Y input and a Z output.
a) Is it a Moore or Mealy machine? Justify.
b) Complete the table of states and outputs (compact table) below
c) How many flip-flops are needed to complete the circuit?
d) If the input Y is kept at 1 and starting from the state (S0), what will be the frequency of the output Z if the clock has a frequency of 1 kHz?
e) Give the sequence Z, if Y = 1 1 0 0 1 1 1 1 1 0 0 0 1 1 1 1 0.
f) Give an assignment that reduces the input combinational circuit.
g) Give an assignment that reduces the input combinational circuit.
0 0 0 %i 0 0 0 0 FIG. 2Explanation / Answer
3) Solution:
a) The given state machine is a moore machine because the outputs are dependent on only present state and independent on the inputs.
b) Based on the state diagram, state table can be derived as,
Present state
Next state
Y(input)
Output Z
Y(input)
0
1
0
1
S0
S4
S1
0
0
S1
S4
S2
0
0
S2
S6
S3
1
1
S3
S6
S0
1
1
S4
S0
S5
0
0
S5
S0
S6
0
0
S6
S2
S7
0
0
S7
S2
S4
0
0
c) Total 8 states are required to represent the control flow of the circuit and three flip flops are required to implement the circuit.
No of flip-flops = 3.
d) If input is kept at 1 and the initial state is S0 then it goes to state S0->S1 ->S2 ->S3->S0 repeats and output is changed as 0->0->1->1->0->0->0->1->1->1 continues. So the frequency of the output is divided by two times the clock frequency.
So output frequency = 500Hz.
e) For the given sequence of inputs, the following output sequence is observed.
Y = 1 1 0 0 1 1 1 1 1 0 0 0 1 1 1 1 0
Assume that the initial state is S0 and Output is 0 1 0 1 1 0 0 1 1 0 1 0 0 0 0 0 0.
f)&g) To reduce the gate count for optimum use of hardware, it is always preferred the adjacent states are assigned with the optimum distance binary coding.
S0 -> 000
S1 -> 001
S2 -> 010
S3 -> 011
S4 -> 100
S5 -> 101
S6 -> 110
S7 -> 111
Present state
Next state
Y(input)
Output Z
Y(input)
0
1
0
1
S0
S4
S1
0
0
S1
S4
S2
0
0
S2
S6
S3
1
1
S3
S6
S0
1
1
S4
S0
S5
0
0
S5
S0
S6
0
0
S6
S2
S7
0
0
S7
S2
S4
0
0
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