3. FETs can be used to either pull an output high or to pull it low, but NFETs a
ID: 2250310 • Letter: 3
Question
3. FETs can be used to either pull an output high or to pull it low, but NFETs are gener- ally better in digital applications for pulling outputs low and PFETs for pulling outputs high. Consider an NFET with characteristics NMOS: k, = 115pA/V2, VTo = 0.43, = 0.06V-1. IosAT = 0.61, W/L = 2, and a supply voltage of V" = 2.0V Say the NFET is used to pull a capacitor high: Voet ov (a) How low can the NFET pul the output voltage and still be turned "on? (b) Considering your answer to part (a) above, what is the highest output voltage, Voutm that will be seen using an NFET as a pull-up? r-0.1, what (c) when the output voltage is within 0.11 of its maximum, l ut state is the NFET in (saturation, cut-off, linear)? (d) What is the current, approximately, through the NFET when VVou-0.1? Now consider the case where the NFET is used to pull a capacitor low. You may assume the same characteristics as the previous problem. Nout NA Ov (a) How low can the NFET pull the output voltage and still be turned "on"? (b) Considering your answer to part (a) above, what is the lowest out put voltage, Vou that will be seen using an NFET as a pull-down? (c) When the output voltage is within 0.1V of its minmum VVat+0.1, what state is the NFET in (saturation, cut-off, linear)? (d) what is the current, approximately, through the NFET when l_'-Vout,mm + 0.1? for pulling an output down low rather than pulling it up high. 5. Given the results of the past two problems above, snmarize why an NFET works betterExplanation / Answer
3. (a) VD - VT. If drain is connected to 0V then output can go low upto 0V but in the circuit drain is connected to 2V and in this case output voltage will rise towards 2V.
(b) To turn On NFET, minimum VGS required is its threshold voltage VT . In the given question VG = 2V and VS is the capacitor voltage. As soon as NFET is Turned ON, voltage at source terminal (VS ) starts rising towards VDD = 2V. But same time VGS continues to decrease as VG - VS is having constant VG but rising VS . Hence the moment VS reaches 1.57 V , VG - VS = 2 - 1.57 = VT =0.43V. Hence further increase not possible as NFET will turn OFF and don't charge the capacitor. NFET turns OFF if VGS - VT < or = 0V.
(c) For Saturation, VDS > VGS - VT.
Above condition can be rewritten as (VD - VS ) > (VG - VS ) - VT . Here VG = VD = 2 V. Hence transistor will continue to be in saturation region till turned OFF.
(d) For Saturation current = Kn' W/L (VGS - VT)2 . neglecting channel length modulation
On substitution , 115 x 10-6 x 2 (2 - 1.47 - 0.43)2 . {Since Vmax = 1.57V then Vs = Vout = Vmax - 0.1 = 1.47V}
We get 2.3uA.
Q 4
(a) 0V
(b) 0V
(c) Linear region. Vout, min = 0V then Vout,min + 0.1V = 0.1V. Hence VDS = VD - VS = 0.1V but VGS = 2V. For linear condition VDS < VGS - VT.
(d) Current in linear region = Kn' W/L [(VGS - VT)VDS - V2DS/2] neglecting channel length modulation.
On substitution 115 x 10-6 x 2[(2-0.43)0.1 - (0.1)2/2] = 34.96uA
Q 5. NFET requires minimum overdrive voltage greater than 0 V to turn ON. Here Overdrive voltage is VGS - VT. Hence NMOS source terminal can't be pulled up above VD - VT. As beyond this transistor gets turned OFF.
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