a) Read documents related with decoders, encoders, multiplexers and demultiplexe
ID: 2291997 • Letter: A
Question
a) Read documents related with decoders, encoders, multiplexers and demultiplexers. Learn their truth tables, cascading of them (At least one of the quiz question may come from this part). b) Read documents related with VHDL and learn the basics of VHDL c) Research into case-when and if-elsif structures in VHDL. Give a short example for each structure and explain how they work? d) Draw block diagram of a 8x1 multiplexer (mux), obtain truth table and write VHDL code. e) Draw block diagram of a 1x8 demultiplexer (demux), obtain truth table and write VHDL code. f) Draw block diagram of a 3x8 decoder, obtain truth table and write VHDL code. g) Draw block diagram of a 8x3 priority encoder, obtain truth table and write VHDL code.Explanation / Answer
Parts a) and b) to read
c) Both case-when and if..elseif are used to evaluate expressions and associate value when the boolean expression returns true.
i) if..else : Include all variables in process (sensitivity) list eg:- process (a,b,c,sel). It realizes combinational logic such as mux. They are executed sequentially with higher priority to earlier statements. Hence, it emulates priority encoded logic.
Syntax :-
if Expr_1 then
Output <= Value1;
elsif Expr2 then
Output <= Value2;
else
Output <= Value3;
end if;
ii) case- when :- The CASE statement usually synthesize to a mux. No "priority" will be inferred from the order of the branches. All possible choices must be included, unless the others clause is used as the last choice.
Syntax :
------------------------------------------------
d) library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Mux8_1 is
port ( A,B,C: in STD_LOGIC;
D0,D1,D2,D3,D4,D5,D6,D7 :in STD_LOGIC;
F: out STD_LOGIC );
end Mux8_1;
architecture BEHAVIORAL of Mux8_1 is
begin
process (A,B,C,D0,D1,D2,D3,D4,D5,D6,D7 )
begin
case (A,B,C) is
when "000" => F <= D0;
when "001" => F <= D1;
when "010" => F <= D2;
when "011" => F <= D3;
when "100" => F <= D4;
when "101" => F <= D5;
when "110" => F <= D6;
when "111" => F <= D7;
when others => null;
end case;
end process;
end BEHAVIORAL;
e) library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dmux1 is
port(f:in std_logic;
s:in std_logic_vector(2 downto 0);
f:out std_logic_vector(7 downto 0));
end dmux1;
architectural behavioral of dmux1 is
begin
f(0)<=f when s="000"else'0';
f(1)<=f when s="001"else'0';
f(2)<=f when s="010"else'0';
f(3)<=f when s="011"else'0';
f(4)<=f when s="100"else'0';
f(5)<=f when s="101"else'0';
f(6)<=f when s="110"else'0';
f(7)<=f when s="111"else'0';
end behavioral;
f)library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder is
Port (x, y, z : in STD_LOGIC;
f : out STD_LOGIC_VECTOR (7 downto 0));
end decoder;
architecture Behavioral of decoder is
begin
with (x,y,z) select
f<="00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when "111",
"00000000" when others;
end Behavioral;
g) library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
entity priority_encoder_8_3 is
port(
y : in STD_LOGIC_VECTOR(7 downto 0);
dout : out STD_LOGIC_VECTOR(2 downto 0)
);
end priority_encoder_8_3;
architecture priority_enc_arc of priority_encoder_8_3 is
begin
dout <= "000" when din(7)='1' else
"001" when din(6)='1'else
"010" when din(5)='1' else
"011" when din(4)='1' else
"100" when din(3)='1' else
"101" when din(2)='1' else
"110" when din(1)='1' else
"111" when din(0)='1';
end priority_enc_arc;
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