Using VHDL vivado compleate this homework assignment Implement a finite state ma

ID: 2291951 • Letter: U

Question

Using VHDL vivado compleate this homework assignment

Implement a finite state machine to represent a vending machine. The rule for this state machine is listed as follows. i. Only one dollar can be put into the vending machine at one time. X represents whether there is a valid input. X=1 means one dollar is put into the vending machine at that time. X=0 means no money is input .

ii. The price for pepsi is 2 dollars.

iii. Y represents whether there is a pepsi output . Y=1 means there is a pepsi from the vending machine. iv. the state can only change at the rising edge.

Create one design source file for the state machine

4. The state transition table is shown as follows STATE So SO $1 S1 NEXT STATE SO S1 S1 SO 0

Explanation / Answer

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity fsm_moore is
port (
      clk : in std_logic;
      rst : in std_logic;
      x    : in std_logic;
      y    : out std_logic
);
end fsm_moore;

architecture behave of fsm_moore is
type state_type is (S0, S1);
signal cur_state, next_state : state_type;
begin
Process1: process (clk) Current State Logic
          begin
            if (clk'event and clk = '1') then
              if (rst = '1') then
                 cur_state <= S0;
              else
                 cur_state <= next_state;
              end if;
           end if;
         end process Process1;

Here output depends upon only on current state, therefore it is Mooore Type FSM

Process2: process (cur_state,x) Next State and output logic
           begin
             case (cur_state) is
               when S0 =>
                     z <= '0';
                     if (x = '0') then
                       next_state <= S0;
                     else
                       next_state <= S1;
                     end if;

               when S1 =>
                     if (x = '0') then
                       next_state <= S1;
                       z <= '0';
                   else
                       next_state <= S0;
                       z <= '1';
                   end if;

          end process Process2;

end behave;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity testbench is
end testbench;

architecture test1 of testbench is
component fsm_moore
port (
      clk : in std_logic;
      rst : in std_logic;
      x    : in std_logic;
      y    : out std_logic
);
end component;
signal clk : std_logic;
signal rst : std_logic;
signal x    : std_logic;
signal y    : std_logic := '0';
begin

DUT : fsm_moore (clk, rst, x, y);

process
begin
      clk <= '0';
      wait for 5 ns;
      clk <= '1';
      wait for 5 ns;
end process;

process
begin
      x <= '0';
      rst <= '0';
      wait for 10 ns;
      rst <= '1';
      wait for 10 ns;
      rst <= '0';
      x <= '1';
      wait for 10 ns;
      x <= '0';
      wait for 30 ns;
      x <= '1';
      wait for 40 ns;
      wait;
end process;

end test1;

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Using VHDL vivado compleate this homework assignment Implement a finite state ma

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