Using VHDL do the following: a) design a simple incrementor. All of the ports ar
ID: 2267458 • Letter: U
Question
Using VHDL do the following:
a) design a simple incrementor. All of the ports are in std_ulogic or std_ulogic_vector type. This design entity will increment the input by 0, 1, 2 or 4 (the value depends on the control input, inc).Here is an example entity declaration for incrementor:
b) Design a simple register. All of the ports are in std_ulogic or std_ulogic_vector type. This design entity will load new data values on the rising edge of the clock if the enable is asserted (‘1’). This design entity includes an asynchronous input that resets the state of the register to all zeros when asserted (‘1’). Here is an example entity declaration for register:
ENTITY Mux2 IS GENERIC (width NATURAL RANGE 1 TO 64 := 8); PORT (In0, Inl IN std ulogic vector (width - 1 DOWNTO 0) O:OUT std ulogic vector (width - 1 DOWNTO 0) Sel IN std_ulogic)i END ENTITY Mux2;Explanation / Answer
1 ) Architecture MUXARC of MUX2 is
begin
process(In1,In0,Sel)
variable v_CONCATENATE : std_logic_vector(width-1 downto 0);
begin
case sel is
when "0" = >v_CONCATENATE <= v_CONCATENATE;
when "1"= > v_CONCATENATE <= v_CONCATENATE+"0000000000000001";
when "2"= > v_CONCATENATE <= v_CONCATENATE+"0000000000000010";
when "3" = > v_CONCATENATE <= v_CONCATENATE+"0000000000000100";
when others => NULL;
end case;
end process;
end MUXARC
2. Architecture REGARC of Reg is
begin
process (Clock,reset,D)
begin
if(reset = '1' ) then Q <= "00000000";
elsif (Clock' event and CLOCK = '1')then
Q <= D;
end if;
end process;
end REGARC;
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