5. A 128 x8 ROM is implemented significant address bits to enable the ROMs on as

ID: 2291118 • Letter: 5

Question

5. A 128 x8 ROM is implemented significant address bits to enable the ROMs on as shown below. The decoder decodes the two most e at a time, depending on the address selected Ag Ao ROM 0 ROM 1 ROM 2 ROM 3 A? 2 Tine-t0-4 line EN EN EN EN 8-bit data bus EN3 (a) Express the lowest address and the highest address of each ROM as hexadecimal numbers. ROMO: Low address - ROM1: Low address ROM2: Low address - ROM3: Low address- High address - High address High address - High address - (b) Assume that a single checksum is used for the entire memory and it is stored at the highest address. Complete the flowchart for testing the complete memory system. START Set a Set sum Read address a hecksum with final XOR sum of data XOR contents of address with previous sum. Update Do they NoIndicate the fault Yes address No data address

Explanation / Answer

Memory

Decoder Inputs

Actual Memory Address Lines

Address in Hex

ROM0 (LOW)

0x00

ROM0 (HIGH)

0x1F

ROM1 (LOW)

0x20

ROM1 (HIGH)

0x3F

ROM2 (LOW)

0x40

ROM2 (HIGH)

0x5F

ROM3 (LOW)

0x60

ROM3 (HIGH)

0x7F

(b)

set n=0, set sum = 0

Last data address = 0x7F = 127