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A simple security system for two doors consists of a card reader and a keypad. A

ID: 2266717 • Letter: A

Question

A simple security system for two doors consists of a card reader and a keypad. A person may open a particular door if he or she has a card containing the corresponding code and enters an authorized keypad code for that card. The outputs from the card reader are as follows: A B No card inserted 1 1 Valid code for door 1 1 0 Valid code for door 2 0 1 Invalid card code 0 0 To unlock a door, a person must hold down the proper keys on the keypad and, then, insert the card in the reader. The authorized keypad codes for door 1 are 101 and 110, and the authorized keypad codes for door 2 are 100 and 011. If the card has an invalid code or if the wrong keypad code is entered, the alarm will ring when the card is inserted. If the correct keypad code is entered, the corresponding door will be unlocked when the card is inserted. Design the logic circuit for this simple security system using 4 x 1 Multiplexers. Your circuit’s inputs will consist of a card code A and B, and a keypad code C, D, and E. The circuit will have three outputs X, Y, and Z. If X or Y is equal 1, door 1 or door 2 will be opened; if Z is equal 1, the alarm sound.

Explanation / Answer

Verilog codes for it

module string (clk, X, rst, Q0, Q1, Q2, Z);
input clk, X, rst;
output Q0, Q1, Q2, Z;
parameter S0 = [0,0,0]; //reset state
parameter S1 = [0,0,1]; //strings ending in ...0
parameter S2 = [0,1,0]; //strings ending in ...01
parameter S3 = [0,1,1]; //strings ending in ...010
parameter S4 = [1,0,0]; //strings ending in ...1
parameter S5 = [1,0,1]; //strings ending in ...10
parameter S6 = [1,1,0]; //strings ending in ...100
reg state[0:2];
assign Q0 = state[0];
assign Q1 = state[1];
assign Q2 = state[2];
assign Z = (state == S3);
always @(posedge clk) begin
if (rst) state = S0;
else
case (state)
S0: if (X) state = S4 else state = S1;
S1: if (X) state = S2 else state = S1;
S2: if (X) state = S4 else state = S3;
S3: if (X) state = S2 else state = S6;
S4: if (X) state = S4 else state = S5;
S5: if (X) state = S2 else state = S6;
S6: state = S6;
default: begin
$display (“invalid state reached”);
state = 3’bxxx;
end
endcase
end
endmodule

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