1) Complete the VHDL code so it creates the state machine below. Two types of co
ID: 2265880 • Letter: 1
Question
1) Complete the VHDL code so it creates the state machine below. Two types of coding are used. First method. Complete the code below that uses the transition equations developed in a previous homework assignment. a. +SV cl Count u+0 library IEEE; use IEEE.STD LOGIC 1164 ALL entity hw13 pl is Port (signal clk, U, reset_n: in STD LOGIC; end hw13 pl; architecture data flow of hw13 pl is signal zero :out STD LOGIC); the registers are numbered like they were in the circuit - diagram. It is more common to use a 1 downto 0 assignment. signal Q : STD-LOGIC-VECTOR(2 downto 1):-Q2 is MSB and Q1 is LSB begin regs: process s begin if clk'event and clk '1' then if reset n 'O then Q '0'); else Q(2) end if; end if end process; zeroExplanation / Answer
Only blank spaces are provided with respective fill ups in sequence. Entire code not written
Q1.
regs : process (clk, reset_n, U) -- for synchronous design, sensitivity list can be only clk
Q(1) <= not Q(1); -- for J = K = 1, Q will toggle
Q(2) <= Q(2) when ((U and Q(1)) or (not U and not Q(1)) = ‘0’) else
not Q(2) when ((U and Q(1)) or (not U and not Q(1)) = ‘1’);
zero <= (not Q(1)) and not Q(2));
Q2.
CURRENT STATE
INPUT
NEXT STATE
OUTPUT
Q2
Q1
U
Q2+
Q1+
Z
0
0
0
1
1
1
0
0
1
0
1
1
0
1
0
0
0
0
0
1
1
1
0
0
1
0
0
0
1
0
1
0
1
1
1
0
1
1
0
1
0
0
1
1
1
0
0
0
state <= next_state;
next_state <= S3;
next_state <= S2;
next_state <= S0;
if U=’1’ then
next_state <= S3;
Zero <= ‘1’ when state = s0 else ‘0’;
CURRENT STATE
INPUT
NEXT STATE
OUTPUT
Q2
Q1
U
Q2+
Q1+
Z
0
0
0
1
1
1
0
0
1
0
1
1
0
1
0
0
0
0
0
1
1
1
0
0
1
0
0
0
1
0
1
0
1
1
1
0
1
1
0
1
0
0
1
1
1
0
0
0
Related Questions
Navigate
Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.