1) In this lab you will design the following data path components at the RTL lev
ID: 2250028 • Letter: 1
Question
1) In this lab you will design the following data path components at the RTL level: Arithmetic Logic Unit (should implement the functions as defined in Table on p. 259 of the textbook) 2-to-1 32-bit Multiplexer 32 32-bit Register File (see Figure 4.7 in the textbook) 16-bit to 32-bit Sign Extender a. b. c. d. 2 Your Verilog modules must adhere to the following interfaces: module alu(input wire [31:0] opl, input wire [31:0] op2, input wire [3:0] ctrl, output reg [31:0]result) endmodule; module twotoonemux(input wire [31:0 input, input wire [31:0 input2, input wire sel, output wire [31:01 outputval); endmodule module registerfile(input wire [4:0] readRegl, nput wire [4:0] readReg2, input wire [4:0] writeReg, input wire [31:0] writeData, input wire reg Write, output reg [31:0] readDatal output reg [31:0] readData2): endmodule module signextend(input wire15:0] inputVal, output wire [31:0] outputVal): endmodule 3) Design a test bench in Verilog to validate each of your modules Submit, through Blackboard, as a zip archive named lastname lab3.zip, the deliverables described below. Use all lower case characters for your filenames.Explanation / Answer
module eightbit_alu (input signed [7:0]a,
input signed [7:0]b,
input [2:0]sel,
output signed [7:0]f,
output ovf,
output take_branch);
reg [7:0]f;
reg ovf;
reg take_branch;
always @(a, b, sel)
begin
f = 0;
ovf = 0;
take_branch = 0;
case(sel)
3'b000 : begin f=a+b;
ovf=(a[7] & b[7] & ~f[7]) | (~a[7] & ~b[7] & f[7]);
end
3'b001 : f=~b;
3'b010 : f=a&b;
3'b011 : f=a|b;
3'b100 : f=a >>> 1;
3'b101 : f=a <<< 1;
3'b110 : begin f=
if (a==b)
take_branch=1;
end
3'b111 : begin f=
if (a!=b)
take_branch=1;
end
endcase
end
endmodule
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