4a. if you have a 4 stage instruction [fetch/decode, execute, memory, write back

Question

4a. if you have a 4 stage instruction [fetch/decode, execute, memory, write back], and each of these stages takes 1.5 clock cycles, how long would this take for 3 instructions on a non-pipelined computer? 4b. Then pipeline these 4 stages in each of your instruction leach stage = 1.5 clock cycles], where you fetch/decode the next instruction as soon as the previous fetch/decode is done. hHw long does this take? FIBS 1. What are three basic steps for Tomasulo's algorithm? 2. Choose your favorite data hazard, explain it, and give a good example 3. If you have no pipeline stall, what is the pipeline speedup for a depth of 3 pipelines? 4. what is one reason that pipelining is hard to implement, and explain with an example

Explanation / Answer

For the non pipelined computer, the processor executes single instruction at a time. So, for a single instruction it takes 1.5 clock cycles x 4 stages = 6 clock cycles. So, for 3 instructions it takes 18 clock cycles.

For the pipelined processor, by the time one instruction passes all the 4 stages, i.e, 6 clock cycles, the next instruction passes 3 stages, i.e, 4.5 clock cycles. So,after 1.5 more clock cycles, the third instruction passes 3 stages. The third instruction takes 1.5 more clock cycle to complete its execution. So, it takes total 6+1.5+1.5=9 clock cycles.

1. In Tomasulo's algorithm, we have 3 stages. a. Issue and read: The instruction is fetched and source operands are read. b. Execute: take theoperands and execute the instruction with operator c. Write result or commit

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