WRITE A VHDL CODE FOR THE FOLLOWING PROBLEM. 3. The state transition diagram bel
ID: 2249734 • Letter: W
Question
WRITE A VHDL CODE FOR THE FOLLOWING PROBLEM.
3. The state transition diagram below is for an autonomous vehicle with two front sensors (Sensorr and SensorL). The sensors are active low. The vehicle defaults to moving forward until one of its sensors is tripped. At that point it backs up and turns in the opposite direction. In addition to the sensors there is an input called timer_done which is a flag that comes from an external timer. The outputs left and right control the motors driving the wheels. A 1 turns the wheel forward and a 0 turns it in reverse. State Left Right Forward Back TurnR 1 0 TurnR TurnlExplanation / Answer
entity autocar is
port (clk, rst : in std_logic;
SensorR, SensorL : in std_logic;
timer_done : in std_logic;
output : out std_logic_vector (1 downto 0)
);
end autocar;
architecture autocar_arch of autocar is
type state_type is (Forward, Back, TurnR, TurnL); --define possible states
signal state, next_state: state_type;
begin
process (clk, rst)
begin
if rising_edge(clk) then
if (rst = ‘1’) then –synchronous reset, active high
state <= Forward;
else
state <= next_state;
end if;
end if;
end process;
process (state, SensorR, SensorL, timer_done)
begin
case state is
when Forward=>
if (SensorR=’0’ or SensorL=’0’) then
next_state <= Back;
else
next_state <= Forward;
end if;
output <= “11”;
when Back=>
if (SensorR=’0’ and timer_done=’1’) then
next_state <= TurnL;
elsif (SensorL=’0’ and timer_done=’1’) then
next_state <= TurnR;
elsif (timer_done=’0’) then
next_state <= Back;
end if;
output <= “00”;
when TurnR=>
if (timer_done=’0’) then
next_state <= TurnR;
elsif (timer_done=’1’) then
next_state <= Forward;
end if;
output <= “10”;
when TurnL=>
if (timer_done=’0’) then
next_state <= TurnL;
elsif (timer_done=’1’) then
next_state <= Forward;
end if;
output <= “01”;
when others => null;
end case;
end process;
end autocar_arch;
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