Part 2: Use the single cycle model above to answer the following questions. 1. C
ID: 2249587 • Letter: P
Question
Part 2: Use the single cycle model above to answer the following questions.
1. Can the sltiu instruction execute correctly with this data path? Why or why not?
The answer to this question is "YES", but I am unsure why.
2. A nori instruction is being proposed. Can this new instruction execute correctly with this data path? Why or why not?
The answer to this question is "NO", but I'm unsure why.
The instructor gave us a hint: Do we have a problem when the immediate value is sign-extended, as it must be when we use the given datapath?
Shift Jump address [31-0] left 2 Instruction 25-0 26 28 PC+ 4 [31-28] Add ul 4 Add result RegDst Jump Shift left 2 MemRead MemtoReg Instruction [31-26] Control ALUO MemWrite ALUSrc RegWrite Instruction [25-21] . Read Read address register 1 Read Instruction [20-16] Read data 1 Read PC Zero ALU ALU result Instruction register 2 [31-0) Read Address data M Write Instruction Instruction [15-11]registe 1Write r data 2 ul memory UI data Registers Write Data data memory gn 32 extend Instruction [15-0] ALU control Instruction [5-0] FIGURE 4.24 The simple control and datapath are extended to handle the jump instruction. An additional multiplexor (at the upper right) is used to choose between the jump target and either the branch target or the sequential instruction following this one. This multiplexor is controlled by the jump control signal. The jump target address is obtained by shifting the lower 26 bits of the jump instruction left 2 bits, effectively adding 00 as the low-order bits, and then concatenating the upper 4 bits of PC+ 4 as the high-order bits, thus yielding a 32-bit address.Explanation / Answer
Q1. sltiu instruction stands for SET ON LESS THAN IMMEDIATE UNSIGNED.
It compares the contents of general purpose register value with the sign extended 16 bit immediate unsigned integer number. If contents of general purpose register is less than 16 bit immediate value than binary '1' is written in destination register else binary '0'.
As can be observed in datapath, ALU result is fed to mux (next to data memory) and in turn mux out is connected to write data signal in Registers block.
A mux between registers and alu provides sign extended immediate value to ALU along with read data 1 as the second operand to alu.
Q2. nori instruction is used to logical nor register contents with immediate 16 bit value. Upper 16 bits [31:16] is filled with binary '0's. In the given datapath zero filling is not shown. Using sign extension may end up with 16 bits of binary 0 or 1. LOGICAL NOR with 1 in msb 16 bits will flip the register actual value.
Related Questions
drjack9650@gmail.com
Navigate
Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.