1. The attached file shows the data sheet for chip 74283 which is a 4-bit carry

Question

1. The attached file shows the data sheet for chip 74283 which is a 4-bit carry look-ahead adder.

(a) Use two 74283 chips to design an 8-bit carry look-ahead adder/subtractor. Note that you can use a block (box) to represent 74283 and then add necessary circuits.

(b) What are the delays (i.e., gate delays) of the last SUM bit and the last Cout bit of this 8-bit machine, respectively?

(c) Based on the circuit designed in (a), can you design a circuit to detect overflow for this 8-bit machine adder/subtractor? If YES, please finish the design for overflow checking, and then go to answer

(d) If you answer NO in (c) above, assuming you can break the chips of 74283, please design the overflow checking circuit.

(e) Will the addition of overflow checking circuit affect the circuit delay?

Explanation / Answer

[1].

(a). It is possible to design an adder and subtractor using IC 7483. If you look at the pindiagrams of the IC {A0,A1,A2,A3,A4,B0,B1,B2,B3} are the inputs. Cin 0 represents the iput carry. Cout 3 represents carryout.

lets see how to design a lookahead carry adder using two 7483 ICs. That is we are cascading two 7483ICs. The first step is to ground Cin0 pin. Their will be a total of 16 inputs starting from {A0,A1,A2,A3,A4,A5,A6,A7 and B0,B1,B2,B3,B4,B5,B6,B7}. The carry out of the fist stage will be the carry in of the second stage. so Cin 0 grounded, Cout 3 is the Cin of second stage and cout 7 is the carry of the last stage.

Sum bits are {S0,S1,S2,S3,S4,S5,S6,S7}. The problem of this circuit is it will work only as either an adder or subtractor at a time. Now the question is how to make it dual function. That is to work adder/subtractor at the same time.

We have to add a single IC chip whose name is IC 7486. This are Exor gates. we have to short one input of all the Exor gates available and this should have to be the input cin0 for the first stage. The circuit works as adder/subtractor according to the bit available on this. That is either 0/1. We will keep the inputs {A0,A1,A2,A3,A4,A5,A6,A7} as it is and inputs {B0,B1,B2,B3,B4,B5,B6,B7} WILL be from the inputs of the IC 7486.

This circuit works in dual function.

(b). The delay of the circuit is the delay of all gates in the circuit. Since exor gates are having very less delay compared to the other gates it can be neglected.

(c). The best way to check the overflow is by designing the circuit using an exor circuit. That is consider the case when we are having a single stage adder circuit. We know Cin0 is the carry in and cout3 is the carry out. Just give this as the input to an exor gate, it will gives the information about overflow. So use an Exor gate at any stage like this to check the overflow mechanism.

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