How do I write a VDHL code for this state machine? ENTITY state_machine IS PORT(

Question

How do I write a VDHL code for this state machine?
ENTITY state_machine IS PORT( clk : IN STD_LOGIC; input : IN STD_LOGIC; reset : IN STD_LOGIC; output : OUT STD_LOGIC_VECTOR(1 downto 0)); END state_machine; ARCHITECTURE a OF state_machine IS TYPE STATE_TYPE IS (s0, s1, s2,s3); SIGNAL state : STATE_TYPE; BEGIN PROCESS (clk, reset) BEGIN IF reset = '1' THEN state <= s0; ELSIF (clk'EVENT AND clk = '1') THEN CASE state IS WHEN s0=> IF input = '1' THEN state <= s1; ELSE state <= s2; END IF; WHEN s1=> IF input = '1' THEN state <= s2; ELSE state <= s3; END IF; WHEN s2=> IF input = '1' THEN state <= s0; ELSE state <= s2; WHEN s3=> IF input = '1' THEN state <= s0; ELSE state <= s4; END IF; END CASE; END IF; END PROCESS;    PROCESS (state) BEGIN CASE state IS WHEN s0 => output <= "00"; WHEN s1 => output <= "01"; WHEN s2 => output <= "10"; WHEN s3=> output<= “11”; END CASE; END PROCESS;    END a; ENTITY state_machine IS PORT( clk : IN STD_LOGIC; input : IN STD_LOGIC; reset : IN STD_LOGIC; output : OUT STD_LOGIC_VECTOR(1 downto 0)); END state_machine; ARCHITECTURE a OF state_machine IS TYPE STATE_TYPE IS (s0, s1, s2,s3); SIGNAL state : STATE_TYPE; BEGIN PROCESS (clk, reset) BEGIN IF reset = '1' THEN state <= s0; ELSIF (clk'EVENT AND clk = '1') THEN CASE state IS WHEN s0=> IF input = '1' THEN state <= s1; ELSE state <= s2; END IF; WHEN s1=> IF input = '1' THEN state <= s2; ELSE state <= s3; END IF; WHEN s2=> IF input = '1' THEN state <= s0; ELSE state <= s2; WHEN s3=> IF input = '1' THEN state <= s0; ELSE state <= s4; END IF; END CASE; END IF; END PROCESS;    PROCESS (state) BEGIN CASE state IS WHEN s0 => output <= "00"; WHEN s1 => output <= "01"; WHEN s2 => output <= "10"; WHEN s3=> output<= “11”; END CASE; END PROCESS;    END a;
01 010-1010-10-010-10- 001 1001-10-0110011 000000 0011111111

Explanation / Answer

-- Note
-- In the table provided, Q1Q0 is the current state while Q1+ Q0+ is the next state
-- The state encoding is as follows
-- A --> 00
-- B --> 01
-- C --> 10
-- don'tcare --> 11
-- In the truth table, the output is Z, which is of 1 bit;
-- But in your code your assign next state to the output i.e your assumming the output
-- to be of 2 bits which is Incorrect, The Corrected code is written below


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity state_machine is
port (
   clk : in std_logic;
   rst : in std_logic;
   X : in std_logic_vector (1 downto 0);
   Z : out std_logic
);
end state_machine;

architecture behavioural of state_machine is
type state_type is (A, B, C, D);
signal cur_state, next_state : state_type;
begin

Process1 : process(clk) -- current state logic
   begin
   if (clk'event and clk = '1') then
   if (rst = '1') then
   cur_state <= A;
   else
   cur_state <= next_state;
   end if;
   end if;
   end process Process1;

Process2 : process(cur_state, X) -- next state logic
   begin
   case (cur_state) is
   when A =>
   Z <= '0';
   if (X = "01") then
   next_state <= C;
   elsif (X = "10") then
   next_state <= B;
   else
   next_state <= A;
   end if;
     
   when B =>
   Z <= '0';
   if (X = "00") then
   next_state <= A;
   elsif (X = "01") then
   next_state <= C;
   else
   next_state <= B;
   end if;
     
   when C =>
   Z <= '1';
   if (X = "10") then
   next_state <= B;
   elsif (X = "11") then
   next_state <= A;
   else
   next_state <= C;
   end if;

   when others => next_state <= A; -- have to assign to 'A' else it is giving compile time error

   end case;
   end process Process2;

Process3: process(cur_state) -- output logic
   begin
   case (cur_state) is
   when A => Z <= '0';
   when B => Z <= '0';
   when C => Z <= '1';
   when others => Z <= '0';
-- have to use others else giving compile time error
   end case;
   end process Process3;

end behavioural;

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