Supposc you have a non-pipclined DLX computer where every instuction takes five

Question

Supposc you have a non-pipclined DLX computer where every instuction takes five cydes to cxocuta You run t the following program the machine where the initial valucs of R3 and R7 are 80 and 0 respectively 4-2+2-5+3+2+2+1 19 points). kop ADDI R7, R7,1 0R3), R7 SUB R3, R3,4 BNEZ R3, Loop What dots this program fragment do1-2 scnterncas) a. b. How many iterations does this loop execute before it exis? Oe iteration is defined as executing all the instructions in the loop once s defined will it take to cxocute the code fragmont on this non-pipclined mechine? us machine is pipelined into ive stages (Fesch Decode, Ereoute, Memoy and Wiwback. Each stage takes one cyele to complee. The machine has so bypass panks and hence all daia hazads ave resolwed b stalling. n addiion, zhe sachine has o brach pei or delay lats and hence al control hazards are also resolved by salling. Branch conditions are ewaluated when the branch instraction reaches the exeonte stage. d. S ow how manv cycles each instruction must sta because it has a hazard with ne rev us instruction b y completing te following t e. fan Instruct on Y sta because some ea ier ist uction X so stalle then do o court tat as n sta or Y. n the last co mn write ei er data or hich aused it to fthe number of stal Dot the sang 2n cuch iteratio·show to common c max across iterations control for cch instruction that stalls, dependirg on the Instruction Number of stall R3 e. How many eyeles does the prgm gment on this pipelined proccssor Take care ths not all terations roqumber cycles to umber of cycics for co irstruction after the frngment ard the the fetch cyele number of the first instruction in the fingment. Also consider the extro cycles after loop exit betore an instruction cun be feoched. fragment on a pipelined proceasor is asthe ben the fetch cycle mumber of the first What would have been the speedup on a hypothetical ideal pipeline that had no stalls vs, a non-pipelined machine? What is the actual speodup for the real pipeline with stalls vs a non-pipelined machine? For parts .oh. assuse thar the mackise has resoed data hazards using data forwading along all incorrect, instnuctions in the pipelise along the mis-predicted path are gmashed and then the correct bypass parhs. Further suppase a branck predietor that always predies ake e branch on every branch instruction is added. When the predieon is correet, no stail is neaded; bw instructions are fetched into the pipeline. ir is How many cycles does the progran take to execute on this improved pipeline? As before, take care that not all iterations may tale an equnl nmber cycles to execute. h. What is the speedup forthis impred rcal pipeline vs a nom-pipclined machine on this

Explanation / Answer

a)Program fragment loops until the R7 register value is incremented to 4.

b)The loop is executed 4 times before it exists(R7 becomes from 0 to 4)

c)for nonpipelined each instruction takes 5 cycles,4 instructions and 4 iterations => Cycles=4*4*5=80

d) ADDI - 1 Stall - Control Hazard(in 2nd Iteration)

SW - 1 stall - Data Hazard(Read after Write)

SUBI - 1 stall - Data Hazard(Read after Write)

BNEZ - 1 stall - Data Hazard(Read after Write)

  

e) for Pipelined Cycles =(#Instrcutions+#Stages -1)*time for 1 stage

=> #Cycles= (4*4+5-1)*1=20(without stalls)

with stalls => 20+(14)=34 cycles

f)Speed up for ideal pipeline = Number of stages = 5

Speed up for real pipeline = 80/34 = 2.35

g)#Cycles(without stalls) = 20

f)Speed up = 80/20= 4

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