Question 2 (Verilog using structural gates): tristate buffers can b implemented

Question

Question 2 (Verilog using structural gates): tristate buffers can b implemented with primitive gates. Assume primitive buffer, inverter, an AND gates are available as: Bufferl (output_portname, input_port_name, enable_port_name) not (output port_name, input_port_name) and (output_port name, input_port_name, input port_name) Write Verilog codes for the following circuits using these primitive gates Please write a test bench to simulate your Verilog code. Include you Verilog code, test bench and simulation waveforms in your solution. -1 I1 I3 I4 Is (a) Eight-bit buffer array I6 I7 SR B0 B B2B3 B4B5 B6 B7 CE AO A A2 A3 A4 A5 A6 A7 (b)Eight-bit bi-directional buffer array

Explanation / Answer

a)

module buffer_array_8bit(I,E,D);

input [8:0] I;

input E;

output [8:0] D;

                Buffer1 B0(D[0],I[0],E);

                Buffer1 B1(D[1],I[1],E);

                Buffer1 B2(D[2],I[2],E);

                Buffer1 B3(D[3],I[3],E);

                Buffer1 B4(D[4],I[4],E);

                Buffer1 B5(D[5],I[5],E);

                Buffer1 B6(D[6],I[6],E);

                Buffer1 B7(D[7],I[7],E);

endmodule

b)

module bi_buffer_array_8bit(A,B,CE,SR);

input CE,SR;

inout [8:0] A;

inout [8:0] B;

wire enable_1;

wire enable_2;

wire not_SR;

                not N1(not_SR,SR);

                AND AND1(enable_1,SR,CE);

                AND AND2(enable_2, not_SR,CE);

                Buffer1 Ba_b0(B[0],A[0], enable_1);

                Buffer1 Ba_b1(B[1],A[1], enable_1);

               Buffer1 Ba_b2(B[2],A[2], enable_1);

               Buffer1 Ba_b3(B[3],A[3], enable_1);

            Buffer1 Ba_b4(B[4],A[4], enable_1);

              Buffer1 Ba_b5(B[5],A[5], enable_1);

     Buffer1 Ba_b6(B[6],A[6], enable_1);

     Buffer1 Ba_b7(B[7],A[7], enable_1);

                  Buffer1 Bb_a0(A[0],B[0], enable_2);

                  Buffer1 Bb_a1(A[1],B[1], enable_2);

                 Buffer1 Bb_a2(A[2],B[2], enable_2);

                 Buffer1 Bb_a3(A[3],B[3], enable_2);

               Buffer1 Bb_a4(A[4],B[4], enable_2);

               Buffer1 Bb_a5(A[5],B[5], enable_2);

     Buffer1 Bb_a6(A[6],B[6], enable_2);

     Buffer1 Bb_a7(A[7], B[7], enable_2);

endmodule

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