Design a circuit that has two input ports: data (8-bit) and reset (1-bit) and tw

Question

Design a circuit that has two input ports: data (8-bit) and reset (1-bit) and two 8-bit output (W1 and W2). After a complete synchronous pulse on reset, in the next eight clocks, the circuit receives eight bytes of data on the data port on every rising edge of the clock. In the ninth clock, the result of the average of all received data bytes, and (LargestData + SmallestData)/2 become available on the output ports (W1, W2) of the circuit.
A. Implement this circuit using a mix of Verilog coding and Quartus II components. Design the datapath of this circuit using Quartus II components and design its controller with Verilog.
B. Run simulation to verify your design.

Explanation / Answer

The Complete HDL Design

DataPath and Controller modules are instantiated. Port connections of the Controller include its output control signals, the op_code input from DataPath and the reset external input. Port connections of DataPath consist of adr_bus and data_bus_in and data_bus_out external busses, op_code output, and control signal inputs

module CPU( reset,clk,adr_bus,rd_mem,wr_mem,data_bus_in,data_bus_out );
input reset;
input clk;
input [7:0]data_bus_in;
output [5:0]adr_bus;
output rd_mem;
output wr_mem;
output[7:0]data_bus_out;
wire ir_on_adr, pc_on_adr, ld_ir, ld_ac, ld_pc, inc_pc, clr_pc, pass_add;
wire [1:0] op_code;
Controller cu ( reset, clk, op_code, rd_mem, wr_mem, ir_on_adr, pc_on_adr,
ld_ir, ld_ac, ld_pc, inc_pc, clr_pc, pass_add );
DataPath dp ( clk, ir_on_adr, pc_on_adr, ld_ir, ld_ac, ld_pc, inc_pc,
clr_pc, pass_add, adr_bus, op_code, data_bus_in, data_bus_out );
endmodule

`define Reset 2'b00
`define Fetch 2'b01
`define Decode 2'b10
`define Execute 2'b11
module Controller (reset, clk, op_code, rd_mem, wr_mem, ir_on_adr,
pc_on_adr, ld_ir, ld_ac, ld_pc, inc_pc, clr_pc,
pass_add );
input reset, clk;
input [1:0]op_code;
output rd_mem, wr_mem, ir_on_adr, pc_on_adr, ld_ir, ld_ac, ld_pc;
output inc_pc, clr_pc, pass_add;
reg rd_mem, wr_mem, ir_on_adr, pc_on_adr, ld_ir, ld_ac;
reg ld_pc, inc_pc, clr_pc, pass_add;
reg [1:0] present_state, next_state;
always @( posedge clk )begin : registering
if (reset )
present_state <= `Reset;
else
present_state <= next_state;
end
always @(present_state) begin : combinational
rd_mem=1'b0; wr_mem=1'b0; ir_on_adr=1'b0; pc_on_adr=1'b0;
ld_ir=1'b0; ld_ac=1'b0;
ld_pc=1'b0; inc_pc=1'b0; clr_pc=1'b0; pass_add=1'b0;
case( present_state )
`Reset : begin
next_state = `Fetch; clr_pc = 1'b1;
end
`Fetch : begin
next_state = Decode ; pc_on_adr=1'b1; rd_mem=1'b1;
ld_ir=1'b1; inc_pc=1;
end
Decode : begin
next_state = `Execute;
end
`Execute: begin
next_state = `Fetch;
case( op_code )
2'b00: begin // lda
ir_on_adr=1'b1; rd_mem=1'b1; ld_ac=1'b1;
end
2'b01: begin // sta
ir_on_adr=1'b1; pass_add = 1'b0;
wr_mem=1'b1;
end
2'b10: ld_pc=1'b1; // jmp
2'b11: begin // add
pass_add=1'b1; ld_ac=1'b1;
end
endcase
end
endcase
end
endmodule

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