BIT COUNTER a) Write test code to run the source code given for ISIM. b) Show re
ID: 2085377 • Letter: B
Question
BIT COUNTER
a) Write test code to run the source code given for ISIM.
b) Show result with at least two different results: one for Data input with 3 bits of 1’s, another one for Data input with 6 bits of 1’s (or explain that this is impossible).
c) Show result with a result of 10 bits of 1’s or explain that this is impossible. Assume that you do not change the code at all.
Plaintext Code
always @(y, A[0])
begin: FSM_outputs
// defaults
EA= 0; LB = 0; EB = 0; Done = 0;
case (y)
S1: LB = 1;
S2: begin
EA = 1;
if (A[0]) EB = 1;
else EB = 0;
end
S3: Done = 1;
endcase
end
// datapath circuit
// counter B
always @(negedge Resetn, posedge Clock)
if (!Resetn)
B <= 0;
else if (LB)
B <= 0;
else if (EB)
B <= B + 1;
shiftrne ShiftA (Data, LA, EA, 1’b0, Clock, A);
assign z = A;
endmodule
Figure 7.20 Verilog code for the bit-counting circuit (Part b).
Explanation / Answer
// Code your design here
module bitcount(Clock,Resetn,LA,s,Data,B,Done);
input Clock,Resetn,LA,s;
input [7:0] Data;
output reg [3:0] B;
output reg Done;
wire [7:0] A;
wire z;
reg [1:0]Y,y;
reg EA,EB,LB;
//control circuit
parameter S1=2'b00,S2=2'b01,S3=2'b10;
always@(s,y,z)
begin:State_table
case(y)
S1: if(!s) Y=S1;
else Y=S2;
S2: if(z==0) Y=S2;
else Y=S3;
S3: if(s) Y=S3;
Y=S1;
default: Y=2'bxx;
endcase
end
always@(posedge Clock,negedge Resetn)
begin:State_flipflops
if(Resetn==0)
y<=S1;
else
y<=Y:
end
always @(y, A[0])
begin: FSM_outputs
// defaults
EA= 0; LB = 0; EB = 0; Done = 0;
case (y)
S1: LB = 1;
S2: begin
EA = 1;
if (A[0]) EB = 1;
else EB = 0;
end
S3: Done = 1;
endcase
end
// datapath circuit
// counter B
always @(negedge Resetn, posedge Clock)
begin
if (!Resetn)
B <= 0;
else if (LB)
B <= 0;
else if (EB)
B <= B + 1;
end
shiftrne ShiftA (Data, LA, EA, 1’b0, Clock, A);
assign z = A;
endmodule
module shiftrne(in,par_load,enable,w,Clk,Q);
parameter n=8;
input [n-1:0] in;
input par_load,enable,w,Clk;
output reg [n-1]Q;
integer k;
always@(posedge Clk)
begin
if(par_load)
Q<=in;
else if(enable)
begin
Q[n-1]<=w;
for(k=n-1;k>0;k=k-1)
Q[k-1]<=Q[k];
end
endmodule
module testbench();
reg Clock;
reg [7:0] Data;
wire [3:0]B
bitcount i1(Clock,1,1,0,Data,B,Done);
initial
$monitor("Data = %b, Done = %b, B = %b, time = %t",Data,Done,B,$time);
initial begin
#100 a = 8'b00011100;
#100 a = 8'b01111110;
#100 a = 8'b11111111;
#100;
end
endmodule
RESULT:
ISim P.20131013 (signature 0x7708f090)
This is a Full version of ISim.
WARNING: For instance testbench/i1/, width 1 of formal port Resetn is not equal to width 32 of actual constant.
WARNING: For instance testbench/i1/, width 1 of formal port LA is not equal to width 32 of actual constant.
WARNING: For instance testbench/i1/, width 1 of formal port s is not equal to width 32 of actual constant.
Time resolution is 1 ps
Simulator is doing circuit initialization process.
Finished circuit initialization process.
Data = xxxxxxxx, Done = x, B = xxxx, time = 0
Data = 00011100, Done = x, B = xxxx, time = 100000
Data = 01111110, Done = x, B = xxxx, time = 200000
Data = 11111111, Done = x, B = xxxx, time = 300000
ISim>
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