42. The Microwind software has never been used to calculate cross-talk in mixed-

Question

42. The Microwind software has never been used to calculate cross-talk in mixed-signal IC design. 43. Parasitic capacitances worsen the frequency response of mixed-signal ICs. This is because pre-layout simulations are more accurate than post-lay-out simulations. 44. Dr. Wagdy created an algorithm for designing the priority encoder of n-bit flash ADCs 45. Microwind can be used to design LO pads. 46. Long wires are worse than short wires in mixed-signal IC design, due to larger transmission delays in the former compared to the latter. 47. Using Microwind alone is better than using both Microwind and Dsch in EE434/534. 48. The definition 0.18um technology means that the polysilicon gate is 0.18 m long. 49. In a mixed-signal IC the digital circuit is always the victim of substrate noise coupling originated by the analog circuit. 50. Using guard rings pulls higher-level noise contours closer to the protected circuit. 51·The interconnect delays become more dominant in deep-submicron CMOS 52. Spice and Verilog are similar in that Spice simulations utilize schematics whereas the 53. To remove power supply noise, a decoupling capacitor is used to kill the ac signal. 54. Power supply pinning for mixed-signal IC design means that both the analog and 55. When connecting a capacitor between the output and the inverting input of an op- Technology as the feature size gets smaller and smaller. Verilog code can be synthesized to generate schematics. digital sections are fed from one conductor connected to a single power pin. amp, the bottom plate should be connected to the inverting input to minimize interference from the substrate. 56. Differential architectures outperform single-ended ones in combating substrate noise 57. A good floor plan for a mixed-signal IC chip should maximize the distance between 58. The bulk of an n-channel or p-channel MOSFET should be connected to the most coupling. digital output drivers and low-amplitude analog circuits within the selected die aea. positive or most negative potential respectively.

Explanation / Answer

42)FALSE

43)TRUE

44)FALSE

45)TRUE

46)FALSE

47)TRUE

48)TRUE

49)FALSE

50)TRUE

51)FASLE

52)TRUE

53)TRUE

54)FALSE

55)TRUE

56)TRUE

57)FALSE

58)TRUE

59)FALSE

60)TRUE

61)FALSE

62)FALSE

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