a) (5 marks) The entity for a full adder is given below. library IEEE; use IEEE
ID: 2084467 • Letter: A
Question
a) (5 marks) The entity for a full adder is given below. library IEEE; use IEEE STD LOGIC 1164. all; entity full adder is port x, y, carry in in std logic sum, carry out out std logic) end full adder; Write a corresponding architecture in behavioural VHDL using VHDL boolean functions b) The entity for a 5 bit adder is given below: library IEEE; use IEEE STD LOGIC 1164. all; entity add 5 is port x, y, ln. std logic vector (4 downto 0) sum out std logic vector (4 downto 0) end add 5 Where x, y and sum should be interpreted as signed binary numbers in two's complement notation i) (4 marks Write a corresponding architecture for add5 in structural form using the "full adder" from part a as the only component. Make sure that the architecture is purely structural (zero marks will be awarded for a behavioural description). Don't forget to declare "full adder" as a component i) (2 marks) What range of decimal numbers can be represented by x, y and Sum iii) (2 marks) ls the value on the sum output always valid? If not, under what conditions is it invalid? iv) (2 marks) If the propagation delays of the full adder component are as follows: From any input to the sum output tpd-sum 2 ns From and input to the carry out output pd-carry out 1 ns With the aid of a diagram, determine the worst case propagation delay for the "add5" implementation, from the x and y inputs to the sum outputExplanation / Answer
a) architecture Behavioral of full_adder is
begin
sum <= x XOR y XOR carry_in ;
carry_out <= (x AND y) OR (carry_in AND x) OR (carry_in AND y) ;
end Behavioral;
b)
i)
architecture Behavioral of 5_BIT_Adder is
-- Full Adder VHDL Code Component Decalaration
component full_adder
Port ( x,y,carry_in : in STD_LOGIC;
sum,carry_out : out STD_LOGIC;
end component;
-- Intermediate Carry declaration
signal c1,c2,c3,c4,c5: STD_LOGIC;
begin
-- Port Mapping Full Adder 4 times
FA1: full_adder port map( x(0), y(0), carry_in, sum(0), c1);
FA2: full_adder port map( x(1), y(1), c1, sum(1), c2);
FA3: full_adder port map( x(2), y(2), c2, sum(2), c3);
FA4: full_adder port map( x(3), y(3), c3, sum(3), c4);
FA4: full_adder port map( x(4), y(4), c3, sum(4), c5);
end Behavioral;
ii) For x,y and sum are 5 bit wide. Hence, the lowest possible combination is 5'b00000.
i.e. decimal 0 and maximum possible combination is 5'b11111, i.e. decimal 31.
iii) When the sum of two numbers crosses decimal 31, it becomes invalid.
iv) For each structural definition, we have 3 inputs. Therefore, total input-sum output delay = 6ns.
Similarly, from total input-carry output = 3ns.
So, for 5 structural instantiations, worst case delay will be (6+3)*5 = 45ns
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