Please rewrite this VHDL code in a different way/method. The goal is to have a n
ID: 2083917 • Letter: P
Question
Please rewrite this VHDL code in a different way/method.
The goal is to have a new code that does the same function as the old one by using a different approach.
library ieee;
use ieee.std_logic_1164.all;
-
entity key_pre is
generic(WITCH : integer := 1);
port(
clock : in std_logic;--ʱÖÓ
KEY : in std_logic_vector(WITCH-1 downto 0);
KEY_p : out std_logic_vector(WITCH-1 downto 0)
);
end key_pre;
architecture rtl of key_pre is
signal KEY_d : std_logic_vector(WITCH-1 downto 0):=(others=>'0');
signal KEY_d1 : std_logic_vector(WITCH-1 downto 0):=(others=>'1');
signal KEY_d2 : std_logic_vector(WITCH-1 downto 0):=(others=>'1');
signal KEY_q1 : std_logic_vector(WITCH-1 downto 0):=(others=>'0');
signal KEY_q2 : std_logic_vector(WITCH-1 downto 0):=(others=>'0');
signal cnt_20ms : integer :=0;
signal clock_20ms : std_logic:='0';
begin
process(clock)
begin
if(clock'event and clock = '1') then
if(cnt_20ms<500000) then
cnt_20ms<=0;
clock_20ms<=not clock_20ms;
else
cnt_20ms<=cnt_20ms+1;
end if;
end if;
end process;
process(clock_20ms)
begin
if(clock_20ms'event and clock_20ms = '1') then
KEY_d1<=KEY;
KEY_d2<=KEY_d1;
KEY_d<=not(KEY_d1 or KEY_d2);
end if;
end process;
process(clock)
begin
if(clock'event and clock = '1') then
KEY_q1<=KEY_d;
KEY_q2<=KEY_q1;
KEY_p<=(KEY_q1 and (not KEY_q2));
end if;
end process;
end rtl;
Explanation / Answer
we can modify above code using a case statement
Modified code is:
library ieee;
use ieee.std_logic_1164.all;
-
entity key_pre is
generic(WITCH : integer := 1);
port(
clock : in std_logic;--ʱÖÓ
KEY : in std_logic_vector(WITCH-1 downto 0);
KEY_p : out std_logic_vector(WITCH-1 downto 0)
);
end key_pre;
architecture rtl of key_pre is
signal KEY_d : std_logic_vector(WITCH-1 downto 0):=(others=>'0');
signal KEY_d1 : std_logic_vector(WITCH-1 downto 0):=(others=>'1');
signal KEY_d2 : std_logic_vector(WITCH-1 downto 0):=(others=>'1');
signal KEY_q1 : std_logic_vector(WITCH-1 downto 0):=(others=>'0');
signal KEY_q2 : std_logic_vector(WITCH-1 downto 0):=(others=>'0');
signal cnt_20ms : integer :=0;
signal clock_20ms : std_logic:='0';
begin
process(clock , clock_20ms)
begin
case clock is
when ( clock'event and clock = '1' ) &( cnt_20ms<500000) =>
cnt_20ms<=0;
clock_20ms<=not clock_20ms;
when ( clock'event and clock = '1' ) & ~( cnt_20ms<500000) =>
cnt_20ms<=cnt_20ms+1;
when (clock_20ms'event and clock_20ms = '1') =>
KEY_d1<=KEY;
KEY_d2<=KEY_d1;
KEY_d<=not(KEY_d1 or KEY_d2);
when (clock'event and clock = '1') =>
KEY_q1<=KEY_d;
KEY_q2<=KEY_q1;
KEY_p<=(KEY_q1 and (not KEY_q2));
end case ;
end process;
end rtl;
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