University of Texas at El Paso Electrical and Computer Engineering Department EE
ID: 2083549 • Letter: U
Question
University of Texas at El Paso
Electrical and Computer Engineering Department
EE 2169 –Laboratory for Digital Systems Design I
Lab Final –State Machine – The Laundry Washing Machine
You are tasked with designing the digital control system of a Laundry Washing machine display (team of 2 students
maximum). Your particular Laundry Machine is designed to perform 3 different wash cycles: Basic, Normal, and
Heavy. The three cycles include:
Basic load
washing
(
bc
):
1.
Wash cycle and dispensing Detergent.
2.
Wash cycle and Spin cycle.
3.
Rinse cycle and Spin cycle.
4.
Spin cycle.
Normal load washing (
no
):
1.
Wash cycle and dispensing Detergent.
2.
Wash cycle and Spin cycle.
3.
Rinse cycle and dispensing fabric Softener.
4.
Rinse cycle and Spin cycle.
5.
Spin cycle.
Heavy load washing (
HY
):
1.
Wash cycle and dispensing Detergent.
2.
Wash cycle and Spin cycle.
3.
Wash cycle and dispensing Detergent.
4.
Wash cycle and Spin cycle.
5.
Rinse cycle and dispensing fabric Softener.
6.
Rinse cycle and Spin cycle.
7.
Spin cycle.
The system should work as follows:
It will be assumed that the laundry detergent and the fabric softener will be previously added on an external container
before starting the machine. Each washing sequence will ONLY initiate when the correct amount of money is inserted.
BTN3 will be used as the input of the accumulated added amount of 25 cents every time is pushed. Every pushed will
add money until the cost for every wash cycle is met:
Basic load washing (
bc
): 50 cents (25¢ + 25¢ = 50¢)
Normal load washing (
no
): 75 cents (25¢ + 25¢ + 25¢ = 75¢)
Heavy load washing (
Hy
): 1 dollar (25¢ + 25¢ + 25¢ + 25¢ = $1.00)
Each time money is added to the machine both Seven Segment Displays (SSDs) will show the amount of money being
deposited:
00
(no money/initial value),
25
(25¢),
50
(50¢),
75
(75¢),
10
($1.00). It won’t allow more than a dollar
to be inserted.
A wash cycle is selected using SW0 (Basic wash), SW1 (Normal wash) and SW2 (Heavy wash). The washing cycle
will only start when the laundry lid sensor detects it’s closed (SW7 = 1). Once it’s closed it cannot be opened until the
full washing cycle is done. Immediately after closing the lid the last digit of the each team’s student ID numbers will
2
be displayed on both SSDs in one clock cycle (For Example, a team has the UTEP IDs 80-210523 and 80-213466 so
this should display the decimal number 3 and 6 on the SSDs:
36
or
63
), then start the washing cycle. That is your
fingerprint intellectual property protection mechanism.
The system should display the selected cycle on both SSDs (
bc
or
no
or
Hy
) and the machine tasks on the LEDs
(LED7, LED6 and LED5) sections of the FPGA. Each tasks will happen at a clock cycle. Please refer to the figure
below for the tasks and use it to define the Finite State Machine diagrams and Truth Tables for the project:
bc
: Lid down
finger printwash/detergentwash/spinrinse/spinspinini
alize
/resetidle/add money
n0
: Lid downfinger printwash/detergentwash/spin
rinse/so
nerrinse/spinspinini
alize
/resetidle/add money
Hy
: Lid downfinger printwash/detergentwash/spinwash/detergentwash/spin
rinse/softnerrinse/spinspin
ini
alize/resetidle/add money
After the machine is done it should reset or return to the initially programed status (SSD =
00
and LEDs = 3’b000). In
summary, assign the buttons and switches on the FPGA as follows:
Add 25 cents BTN3
Washer Lid open SW7
Basic cycle SW0
Normal cycle SW1
Heavy cycle SW2
A few notes on the implementation:
3
1.
Assume that only
one
button and switch for the washing cycle can and will be pressed at a time. No need to
account for multiple inputs being on.
2.
Use the CLK signal used in Labs 7 and 8 as your synchronizing clock with a frequency f = 0.5 HZ
Explanation / Answer
Solution:
Digital control system of a Laundry washing machine
Let we design the digital system using VERILOG Code.
VERILOG Code:
module laundry_washing_machine (Clock, SW1,SW2,SW3,SW7,BTN3,Student1,Student2,7_1,7_2);
input SW1;
input SW2;
input SW3;
input SW7;
input Clock;
input BTN3;
input Student1;
input Student2;
output 7_1;
output 7_2;
integer Student1,Student2;
register [6:0] 7_1,7_2;
register ab = 0;
register cd = 0;
register ef = 0;
register disp_id = 0;
register last_state = 0;
integer count_cent = 0;
integer bcd_t1,bcd_t2;
integer count_state = 0;
integer count_cent = 0;
integer count_state_term = 0;
always@(posedge SW1) begin
if(last_state == 0)
begin
ab = 1;
last_state = 1;
end
end
always@(posedge SW2)
begin
if(last_state == 0)
begin
cd = 1;
last_state = 1;
end
end
always@(posedge SW3)
begin
if(last_state == 0)
begin
ef = 1;
last_state = 1;
end
end
always@(posedge BTN3)
begin
count_cent = count_cent + 1;
if( count_cent == 1) begin
bcd_t1 = 2;
bcd_t2 = 5;
end
else if( count_cent == 2) begin
bcd_t1 = 5;
bcd_t2 = 0;
end
else if( count_cent == 3) begin
bcd_t1 = 7;
bcd_t2 = 5;
end
else if( count_cent == 4) begin
bcd_t1 = 1;
bcd_t2 = 0;
end
else
$display("Invalid");
if(ab == 1)
disp_id = 1;
else if (cd == 1)
disp_id = 1;
else if (ef == 1)
disp_id = 1;
end
always@(posedge SW7)
begin
if(disp_id == 1)
bcd_t1 = Student1%10;
end
always@(posedge SW7)
begin
if(disp_id == 1)
bcd_t2 = Student2%10;
end
always@(bcd_t1) begin
case(bcd_t1)
1: 7_1 = 7'b1001111;
2: 7_1 = 7'b0010010;
5: 7_1 = 7'b0100100;
7: 7_1 = 7'b0001111;
0: 7_1 = 7'b0000001;
default : 7_1 = 7'b0000000;
endcase
end
always@(bcd_t2) begin
case(bcd_t2)
5: 7_2 = 7'b0100100;
0: 7_2 = 7'b0000001;
default : 7_2 = 7'b0000000;
endcase
end
always@(negedge SW7)
begin
#100;
if (ab == 1)
count_state_term = 5;
else if (cd == 1)
count_state_term = 5;
else if (ef == 1)
count_state_term = 7;
while ( count_state <= count_state_term )
begin
@(posedge Clock);
count_state = count_state + 1;
end
last_state = 0;
end
always@(posedge Clock)
begin
if (ab == 1) begin
7_1 = 7'b1100000;
7_2 = 7'b1110000;
end
else if (cd == 1)
7_1 = 7'b1101010;
7_2 = 7'b0000001;
end
else if (ef == 1)
7_1 = 7'b1001000;
7_2 = 7'b1000100;
end
end
always@(negedge last_state )
begin
count_state = 0;
count_cent = 0;
count_state_term = 0;
ab = 0;
cd = 0;
ef = 0;
end
endmodule
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