An ARM processor with 32-bits address and data buses is connected to three areas

Question

An ARM processor with 32-bits address and data buses is connected to three areas of memory implemented as three types of chips. The address is a byte address.

- A 256M Byte EEPROM implemented using EEPROM chips that are 32Mx16-bits

- A 256M Byte SRAM implemented using two chip types:

* SRAM 16Mx32-bit memory chips

* SRAM 32x8-bit memory chips

Answer the following questions for every category of chips:

1. Determine the number of address lines that the chip will have as inputs and give them names (Axx-Ayy).

2. Determine the number of chips required to build the corrosponding subsystems. Given that we have only 4 chips of the 32Mx8-bits and that thesemust be used

3. List the control signals needed inevery chip and name them.

* EEPROM: 16-bit databus, i.e. 2 bytes each could be accessed seprately or both as a single word

* SRAM 16Mx32-bit data bus, with possibility of accessing eachbyte separatly.

* SRAM 32Mx8-bit data bus

4. Given that the start addresses for the two memory blocks are shown in the table below, fill in the table by computing the end addresses of these memory blocks

block start address block end address

SRAM 0000_0000b

Flash EEPROM

5. Show the decoding (equations only) of the global CEb signals, namely SPRAM_CEb and EEPROM_CEb, corrosponding to the two blocks. These signals are active low.

6. Because memory is byte addressable, using a decoder and some gates draw the circuit that generates the OEb signal(s) and the WEb signal(s). Note that these signals are active low. You will also need the following signals.

BWb. Indicates whether the current access is a Byte (0) or a Word (1) access

BWb: Indicates whther the current access is a Read (0) or a Write (1)

Explanation / Answer

1) 1024*8 means that you have:

Address Lines:

Assuming that number of address lines (address bits) is n, how can we find n? If n=1, you can only address 2 locations (0 and 1). If n=2, you can address 2 locations (0, 1, 2, and 3). As you can see, number of addressable locations = n^2.
Given that number of addressable locations = 1024, then 1024=2^n
This means that n=log(1024) to the base 2.
Thus, n=10.

Data Lines:

You have 8 bits for every location, therefore your memory needs a data bus with 8 lines. Every time you read a location (by loading its address on the address bus), the 8 bits that are stored at that location are loaded (by the memory chip) on the 8-line data bus.

Memory size:

As obvious, your memory has 1024*8 bits (8192 bits). Or simply, 1024 bytes

2) 1M = 1024k size of new ram = (1024k *4) no of chips required = (1024*4)/(256*1) = 16

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