Design a finite state machine (FSM) that cycles through the last 4 digits of you

Question

Design a finite state machine (FSM) that cycles through the last 4 digits of your UTEP student ID in a loop. In your design there should be an input that changes the direction of the cycle. Each number of the ID should be displayed on the seven-segment display while the current state of the FSM should be displayed on its corresponding LED. Non-valid states should keep all LHDs off. Use the clock used in Lab 7 as the synchronizing clock signal. For Example, a particular student has the UTEP ID 80-210543. The state diagram and outputs for his design are as follows: Draft the behavioral Verilog module for the FSM.

Explanation / Answer

module seq_dect
(
input clk, data_in, reset,
output reg [7:0] data_out // Seven segement Out : abcd_efgh
);
// Declare state register
reg [2:0]state;
// Declare states
parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3;

// Determine the next state
always @ (posedge clk or posedge reset) begin
if (reset)
state <= S0;
else
case (state)
S0:
if (data_in)
state <= S1;
else
state <= S3;
S1:
if (data_in)
state <= S2;
else
state <= S0;
S2:
if (data_in)
state <= S3;
else
state <= S1;
S3:
if (data_in)
state <= S1;
else
state <= S2;
  
endcase // case (state)
end // always @ (posedge clk or posedge reset)
// Output depends only on the state
always @ (state) begin
case (state)
S0:
data_out = 8'b1111_1100;     // Display '0'
S1:
data_out = 8'b1011_0110;   // Display '5'
S2:
data_out = 8'b1011_0110;   // Display '4'
S3:
data_out = 8'b1111_0010;   // Display '3'   
default:
data_out = 8'b0000_0000;   // Display nothing error state
endcase // case (state)
end // always @ (state)

endmodule

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