Design a common source amplifier with a mid-band voltage gain of at least – 4 vo

Question

Design a common source amplifier with a mid-band voltage gain of at least – 4 volts/volt, and a lower 3-db frequency of 400 Hz. The power supply is 12.0 volt, the load resistance is 1.0 kohms

2.     Use 1/3 voltage rule and assume any drain current in mA.

3.     Plot gain and power vs. frequency

4.     From the gain determine the lower and upper 3-db frequencies and the bandwidth

5.     Determine the mid-band gain.

6.     Determine the power at the 3-db frequencies as well as the power at mid-band gain.

Explanation / Answer

• A discrete common source amplier can be constructed that is very similar in
form to a common emitter
• Biasing with a current source is quite common, particularly for ICs
• But IC ampliers do not include decoupling/bypass capacitors and biasing
resistors
VDD
RG
RD
-VSS
C1
C2
C3
RL
v
s
ILecture 22-2
Common Source Amplier
• Design the amplier for maximum possible output voltage swing
VDD
RG
RD
-VSS
C1
C2
C3
RL
=10k
v
s
I=1mA
K=0.25mA/V
2
Vt
=2V
VDD=10V
RG=500k ( >> RS
)
RS
=0.02Lecture 22-3
Common Source Amplier
VDD
RG
RD
-VSS
C1
C2
C3
RL
=10k
v
s
I=1mA
K=0.25mA/V
2
Vt
=2volts
VDD=10volts
RG=500k ( >> RS
)
RSLecture 22-4
Common Source Amplier
• Analyze the circuit --- rst solve for the dc bias point:
M1-NMOS
L=10U
W=10U
D
S
C1
1UF
+ -
RD
6K
C2
1UF
+ -
+ 10V
VCC
+
-
VOUTAC
0.000 pV
+ -10V
VSS
C12
1UF
+ -
IC
1.000 mA
+ SIN
VSSIN
+
-
VIN
0.000 pV
1mA
IS
RL
10K
+
-
VD
4.000 V
RG
5E5
+
-
VS
-3.837 VLecture 22-5
Small Signal Model
VDD
RG
RD
-VSS
C1
C2
C3
RL
v
s
I
g
m
v
s
G
S
D
vs
RG r
o
RD RLLecture 22-6
Small Signal Model
g
m
v
s
G
S
D
v
s
RG r
o

ac Response
• Frequency response with lamda=0.02
frequency
e2 e3 e4 e5 e6 e7
5
6
7
8
9
10
11
12
DB(VOUTAC/VIN)Lecture 22-8
Transient Response
• Time-domain response for a 10kHz, 0.2v peak ac input signal with
lamda=0.02
time
0.0 0.1 0.2 0.3 0.4 0.5 0.6 ms
-1
0
1
V
VOUTAC VINLecture 22-9
Transient Response Distortion?
• Vin multiplied by the midband gain, and shifted in phase by 180°
demonstrates that there is very little distortion
time
0.0 0.1 0.2 0.3 0.4 0.5 0.6 ms
-1
0
1
V
VOUTAC VIN VIN*(-3.75)Lecture 22-10
ac Response
• Response for a 10kHz, 0.2v peak ac input signal with lamda=0
• How can we change the design so that lamda is practically zero?
frequency
e2 e3 e4 e5 e6 e7
5
6
7
8
9
10
11
12
DB(VOUTAC/VIN)Lecture 22-11
Improving the Gain
• Assuming that the peak ac output is less than 1.0 volt, we can use a larger
value of RD to increase the gain but still keep the transistor out of the triode
region
M1-NMOS
L=10U
W=10U
D
S
C1
1UF
+ -
RD
10K
C2
1UF
+ -
+ 10V
VCC
+
-
VOUTAC
0.000 pV
+ -10V
VSS
C12
1UF
+ -
IC
1.000 mA
+ SIN
VSSIN
+
-
VIN
0.000 pV
1mA
IS
RL
10K
+
-
VD
0.000 pV
RG
5E5
+
-
VS
-3.920 VLecture 22-12
Improving the Gain
frequency
e2 e3 e4 e5 e6 e7
8
9
10
11
12
13
14
DB(VOUTAC/VIN)Lecture 22-13
Improving the Gain
time
0.0 0.1 0.2 0.3 0.4 0.5 0.6 ms
-1
0
1
V
VOUTAC VIN VIN*(-4.7)
• But further increase in RD
is not possibleLecture 22-14
Current Mirrors
R
3.3V
M1 M2Lecture 22-15
Current Mirrors - Output Resistance
R
3.3V
M1 M2
IREF I
o
IDLecture 22-16
Current Mirrors-Accuracy
R
3.3V
M1 M2
IREF I
o
IDLecture 22-17
Current Steering
R
3.3V
M1 M2
IREF I
2
ID
M3
I
5
M4 M5
I
4
I3
V
SG5
+
-

sorry i designed the circuit but its not getting converted into better format. those figures that are not understandable are figures.

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