Dear Expert, I need help answering these questions Embedded Systems EEL 4742 Hom

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Dear Expert,

I need help answering these questions

Embedded Systems EEL 4742 Homework 4: The ARM v7-M Architecture For the purposes of this homework, you will be examining the ARM architecture. ARM Holdings the company behind the architecture, is a fabless semiconductor company. That is, ARM Holdings does not fabricate or sell processors, instead they license their processor IP to other vendors for them to design and fabricate system on chips. Customers of ARM Holdings include Atmel, Ap ple, Freescale, nVidia, Qualcomm, Samsung, STMicroelectronics, Texas Instruments, and Toshiba Customers are allowed to extend ARM Holdings' original design adding new architectural elements For example, Tegra X1 chips by nVidia include four ARM Cortex-A57 cores alongside four ARM Cortex-A53 cores operating in big. LITTLE model, a Maxwell-based GPU (this type of GPU is also found in the GeForce GTX 970), and hardware accelerators for video encoding and decoding, among other peripherals Currently, ARM Holdings divides their processor lineup into the Cortex-A series, Cortex-R series and Cortex-M series. The Cortex-A series are application processors. These are fully featured processors that include the full ARM instruction set and extensions and a memory management unit. The Cortex-R, series are processors which have been optimized for real-time and safety critical applications, providing extra features such as error-correcting code (ECC) at the L1 cache and busses and fault tolerance The Cortex-M processors are designed for microcontroller usage These cores usually work with the reduced Thumb and Thumb-2 instruction sets, and most CPU peripherals such as the memory protection unit are optional In this homework, you will be looking at the ARM Cortex-M4 processor core. The ARM Cortex- M4 processor is based around the ARM v7-M architecture. Current system on chips utilizing this processor core include the Texas Instruments MSP432P401R, which combines the traditional MSP430 peripherals with some ARM-specific peripherals, and a Cortex core. To answer the following questions, you should look at the documents ARM Cortez-MA Processor Technical Reference Manual, ARM v7-M Architecture Reference Manual, and any other resources in ARM Holdings' website

Explanation / Answer

Integer Register File: It provides single port, two port and ultra high density . two port register file compilers in variety of different architectures that support wide performance range for all types of soc designs. It is used for the temporary storage of information, Register file memory provides higher performance and better area utilization for smaller memory size than standard SRAM memory.it provides read/write ports which are available in PORT-1 AND PORT-2.ARM Register file memory IP typically finds usage in L1 cache solutions, temporary buffers and smaller memory instances are required in an soc design

Advantages over arm mode over thumb 2 mode:

It is 32 bit instruction set it is powerful and provides good performance than thumb mode . It has larger program memory compared to 8 and 16 bit processor.

Advantages over thumb2 mode over arm mode:

16 bit instruction set .It provides a subset of the ARM instructions.It gives better code density chitectureompared to 32 bit RISC architecture. code size is reduced by 30% but performance is also reduced by 20%

A MULTIPLEXER is used to switch between arm and thumb state. using multiplexer it switches between two states which requires a switching head

Floating Point Unit :It supports single precision add subtract , Multiply, Divide and Accumulate & Square root operation. It Provides conversions between fixed point and floating point formats and floating point constant instructions.The FPU provides an extensiion register file containing 32 single- precision registers.they are

Sixteen 64- bit doubleword registers, D0-D15

It contains 32 bit single word registers, s0-s31

NVIC :

The NVIC provides configurable interrupt handling abilities to the processor. It facilitates low-latency exception and interrupt handling and it controls power management.

It Supports upto 240 interrupts each with upto 256 levels of priority. we can change the priority of an interrupt dynamically. The processor fully implements the Wait For Interuppt, Wait For Event and the Send Event instructions. It also supports the SLEEPONEXIT IT CAUSES the processor core to enter sleep mode when it returns from an exception handler to thread mode.

Memory Protection Unit: The MPU regsters are located at 0xE000ED90. There are five basic registers they are

MPU TYPE: address is given by 0xE000ED90 . It contains the numberb of regions in bits and 0 for no MPU.

CONTROL REGISTER: address is gven by 0xE000ED94. It controls the enabling and disabling of the MPU

REGION NUMBER: It selects the region which you want to configure address is given by 0xE000ED98.

REGION BASE ADDRESS: It sets or reads thebase address of region. address is given by 0xE000ED9C.

REGION ATTRIBUTE AND SIZE: It sets or reads the sixe and permissions of region address is given by 0xE000EDA0

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