port ( ____________: __________________________________; ____________: _________
ID: 2081597 • Letter: P
Question
port
( ____________: __________________________________;
____________: __________________________________;
____________: __________________________________
);
END ___________;
ARCHITECTURE ________OF _________ IS
_________
process(____________)
_______
if ________then_______ ;
elsif_______then______ ;
elsif_______then______ ;
else______ ;
______;
end process;
END _________;
S DEMUX abcd . 2 XExplanation / Answer
DEMUX: Demultiplexer is counter of multiplexer. based on the selecton inputs it switches the corresponding output,
if s= "00" the input 'x' swithes to output 'a' , if s= "01" the input 'x' swithes to output 'b' ,
if s= "10" the input 'x' swithes to output 'c' and if s= "11" the input 'x' swithes to output 'd'
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
# Entity declaration with demux1to4 entity name
entity demux1to4 is
port(
x : in STD_LOGIC;
s : in STD_LOGIC_VECTOR(1 downto 0);
a,b,c,d : out STD_LOGIC_VECTOR;
);
end demux1to4;
architecture demulx1to4_arch of demux1to4 is
begin
demux : process (x,s) is
begin
if (s="00") then
a <= x ;
elsif (s = "01") then
b<= x;
elsif (s="10") then
c <= x ;
else
d <= x;
end if;
end process demux;
end demux1to4_arch;
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