a.) what registers and bits are used to ENABLE interrupt on PORT P, bit 5. Confi

Question

a.) what registers and bits are used to ENABLE interrupt on PORT P, bit 5. Configure bit 5 of PORT P to enable interrupt on it.

b.) After interurpt on bit 5 of PORT P is enabled, what additional bit must be set to assert IRQ on bit 5 of PORT P. What causes this bit to be set ?

c.) Descrie the steps that follow a valid IRQ on bit 5 of PORT P, before the ISR can be executed.

HCS12 and Please give detail solution

STS points points Summary of Port P Control Registers Port P Input Reg. PTIP $0259 Data Direction Re DDRP $025A Reduced Drive Control Reg. RDRP $025B Pull Up/Down Enable Reg. PERP S025C Polarity Select Reg. PPSP S025D Port P Interrupt Enable Reg. PIEP S025E Port P Interrupt Flag Reg. $025F

Explanation / Answer

Pin 5 of Port P should receive an interrupt as an input from that device. The microcontroller should identify the event of interrupt being raised and then take required actions/execute the corresponding interrupt service routine. Hence, interrupt should be enabled at P.5 (port p pin 5) i.e., the bit corresponding to pin 5 should be set in the PIEP register.

DDRP = 0x00;    // 8-bits of DIP input (PORT P1 – if the interrupt is receved as an input)(optinal)

PPSP = 0x00;      // pull-up pins PP7-PP2,PP0; define falling-edge trigger for Port P5(optional)

PERP = 0xFF;    // enable pulls (optional)

PIFP = 0x10;      // clear the PORT P Interrupt Flag for PORT P5 before enabling. This is to ensure that ISR is not //executed due to pre existing values at bit 5 of port P.

PIEP = 0x10;   // PP1 = enable interrupt (mandatory)

Now whenever the interrupt at pin 5 of port p is raised, the interrupt flag is set or asserted, the program jumps to the interrup service routine. Within the ISR,

PIFP = 0x10; // Because now that we are handling the interrupt, we can again clear the flag for the next instance of the interrupt. Hence, after our program jumps to the ISR, again set the flag to 1 in order to clear it.

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