ECT357 – HW4 Sequential Circuit Applications Answer all questions fully, making
ID: 2080761 • Letter: E
Question
ECT357 – HW4
Sequential Circuit Applications
Answer all questions fully, making sure to show all work for full credit.
1.The ALU developed in HW3 is going to be updated to include an output interface to the 7-segment displays on the BASYS 2 development boards. Follow the steps below to update the ALU. The final design must be implemented using Verilog code within the Xilinx WebPack IDE.
a.The ALU designed in HW3 must be grouped into a single module named “ALU”. This module will be instantiated into a top-level module named “Processor” as shown in the block diagram displayed in Figure 1. The modified ALU must be implemented using Verilog code within the Xilinx WebPack IDE for credit. (15 pts.)
b.A new module named “Display” must be developed for the processor system and connected to the ALU as shown in Figure 1. This module is responsible for controlling the 7-segmant displays. The display is to show the input operands ‘A’ and ‘B’ and the output value ‘Y’ as shown in Figure 2. Recall that the update rate for the 7-segment displays must be between 1kHz and 60Hz for the displays to appear continually lit. The “Display” module must be implemented using Verilog code within the Xilinx WebPack IDE for credit. (30 pts.)
Figure 1: Block diagram for processor system being developed
Figure 2: Signal mapping for 7-segmant displays
2.The Digilent BASYS2 development board pin assignments for the complete system are listed in Table 1. Note that the input values A and B and the output value Y are to be displayed on the 7-segment displays. Demonstrate the operation of your ALU on the BASYS 2 board to the instructor for credit. (15 pts.)
Table 1: Pin mapping for processor system to BASYS board
3.Develop a Verilog testbench to validate the designed ALU and implement it using Xilinx WebPack. Include the testbench code and associated results for full credit. (20 pts.)
BT LK ALU 7-Seg Display AN CA ovfExplanation / Answer
timescale 1ns/1ps
module alu_tst;
reg [3:0] a,b;
reg [1:0] c_log_arith;
wire [3:0] op;
alu u1 (.op(op), .a(a), .b(b) , .c_log_arith(c_log_arith));
initial
begin
a=4'b0011;
b=4'b1101;
c_log_arith=2'b00;
#100;
a=4'b1101;
b=4'b1111;
c_log_arith=2'b01;
#100;
a=4'b0011;
b=4'b1100;
c_log_arith=2'b10;
#100;
a=4'b1110;
b=4'b0100;
c_log_arith=2'b11;
#100;
a=4'b0111;
b=4'b1001;
c_log_arith=2'b00;
#100;
a=4'b1111;
b=4'b1111;
c_log_arith=2'b01;
#100;
a=4'b1011;
b=4'b1101;
c_log_arith=2'b10;
#100;
a=4'b1110;
b=4'b0111;
c_log_arith=2'b11;
#100
$stop;
end
endmodule
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