The enable input of a D-type latch is used to control the tri-stateable Q output

Question

The enable input of a D-type latch is used to control the tri-stateable Q output control when the Q output equals the D input prevent metastability initialize the Q output to logic '0' A counter has the count sequence 0, 5, 9, 122, 14, 0, 5, 9, ... How many registers does this counter require? 6 7 8 122 The outputs of a ring counter have a 50% duty cycle. TRUE FALSE Which of the following is the count sequence of a modulo-5 counter? 0, 1, 2, 3, 4, 0, 1, ... 0, 1, 2, 3, 4, 5, 0, ... You are using a 54HC160 counter as a modulo-7 counter. What is the output o the counter when the clear input is asserted? 8 7 6 5

Explanation / Answer

5) option a

6) This require 7 resigisters since maximum count = 122 (nearest to 128 = 2^7) option B

7)False. Output neednot be 50%

8) option a shows mod5 counter

9)option b . At 7th count clr should be initiated

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