2nd part only Consider the following asynchronous counter constructed with T FFs

Question

2nd part only

Consider the following asynchronous counter constructed with T FFs: (a) Draw the waveform for the clock and the output of four FFs. (b) Describe the operation of this counter. (c) Design a synchronous counter that performs the same task and derive the VHDL code accordingly. Assume the flip-flops used for the previous problem, (i.e. text problem 9.2) have the following timing parameters: Tcq = 3 ns, Tinv = 7ns, Tsetup = 1 ns. a) Determine the minimum clock period of the circuit from 9.2 (a). Your result should identify the minimum clock period in which the output, signal y, can be registered by another flip-flop that uses the "clk" signal for its clock input b)Determine the minimum clock period of the synchronous circuit you created in 9.2 (c). You will need to make some assumptions on the timing of your next state logic to complete this problem. Clearly state these assumptions when completing this problem.

Explanation / Answer

A) Tclk>tcq+tsetup, Tclk>3ns+1ns, Tclk>4ns. Here we don't consider delay of inverter because it delay is not effecting data input of next flip flop however clock is delayed by inverter delay.

B) if you are using synchronus counter using d fli flop and some combination logic. Where tpd is delay of combination logic. Tclk>tcq+tsetup+tpd

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