Problem 2.60 in the textbook. Problem 2.64(a) in the textbook. Assume both f1 an

Question

Problem 2.60 in the textbook.

Problem 2.64(a) in the textbook. Assume both f1 and f2 are outputs of a single module.

Write Verilog code to describe the multiplexer circuit in Figure 2.33 as a module using if-else statement.

Please note that Verilog requires that procedural statements be contained inside an always block. Besides, signals that are assigned values using procedural statements should be declared a register (i.e., reg).

1 3 4 10 x 1x2x4 The function f( x4) h, Figure 2.59 Em 0, 2, 4, 5. 10, 11.13, 15). x1x2 3 00 01 11 10 (R, x3) (Rit x2) POS minimization of f(xi, x2,x) TM (4, 5, 6) Figure 2.60 that have to be combined into sum terms that are as large as possible. Again, a sum considered larger if it covers more maxterms, and the larger the term, the less costly implement.

Explanation / Answer

According to the given data

first we have to know about

module mux8_1
input [7:0]I;
output [2:0]x;
output a;
input en;
reg a;
always @(en,x,I,a);
begin
if (en= =1)
begin
if (x= =000 a=I[0];
else if (x==001) a=I[1];
else if (x==001) a=I[2];
else if (x==001) a=I[3];
else if (x==001) a=I[4];
else if (x==001) a=I[5];
else if (x==001) a=I[6];
else if (x==001) a=I[7];
end
else a=0;
end
end
end module

16:1 mux code

module mux161 (input [3:0] s, input [15:0] a, output y);

  

assign y=(s==0)? a[0]:

(s==1)? a[1]:

(s==2)? a[2]:

(s==3)? a[3]:

(s==4)? a[4]:

(s==5)? a[5]:

(s==6)? a[6]:

(s==7)? a[7]:

(s==8)? a[8]:

(s==9)? a[9]:

(s==10)? a[10]:

(s==11)? a[11]:

(s==12)? a[12]:

(s==13)? a[13]:

(s==14)? a[14]:a[15];

end

end module

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