4. The circuit shown in schematic (a suffers distortion, as depicted in the simu
ID: 2079292 • Letter: 4
Question
4. The circuit shown in schematic (a suffers distortion, as depicted in the simulat results below. The circuit shown in Schematic (b) is a solution to this problem. The opamps are NOT ideal, but have the specifications listed in the attached datasheet. i) Which op-amp non-ideality is causing the distortion present in (a)? (5 points) ii Show analytically why this non-ideality is causing distortion. (10 points) iii) Show analytically why this distortion is avoided in (b). (10 points) out 1 MHz 1 MHz 200 k 200 k 1 V 1 V 100 k 100 k 1 uF out 0.5 0.5 time (u s) time (u s)Explanation / Answer
1. It is the slew rate of the op-amp that is causing the distortion in the output shown in a.
2. Slew rate of an amp is defined as the rate of change of output caused by changes in input. In this case, the output is unable to reach the expected max output voltage as per the gain of the opamp because the slew rate is limiting the output. Theoretically,
Slew rate = 2*Pi*f*V where f=frequency of the signal, V = Maximum peak voltage of the signal.
In this case, the required slew rate for this signal would be = 2 * 3.14 * 1 * 10e6 * 2 =12.56V/uS
However, the slew rate as per the specification is 5 V/ uS. Hence the signal is getting clamped.
3. The capacitors within the chip reduce the slew rate and cause this clamping issue. The rate of change of output voltage dVo/dt = Current of the output stage / Total capacitance.
If we have to increase the slew rate, ie., increase dVo/dt, then Total capacitance has to be reduced. This is what has been done in (b). The external capacitance connected, reduces the total capacitance and thus improves the slew rate. When the slew rate improves, we can get the entire output signal.
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