As an engineer, you should have knowledge of contemporary issues. Also, you shou
ID: 2072754 • Letter: A
Question
As an engineer, you should have knowledge of contemporary issues. Also, you should have the broad education necessary to understand the impact of engineering solutions in a global, economic, environmental, and societal context
1-Name two contemporary issues that have global importance.
2-Name one contemporary issue or problem that FPGA’s can help address.
3-How do FPGA’s make designs more economical?
4-Either through their capabilities or using an example of the products, components, or systems they are used in, explain how designs containing FPGA’s are good for the environment?
5-Either through their capabilities or using an example of the products, components, or systems they are used in, describe the impact the use of FPGA’s has on society as a whole?
6-Give an example of the global impact of the use of FPGA’s
Explanation / Answer
Sol:
1. I) Preventing Nuclear proliferation
II) Mitigating and Adapting to climate change
III) Managing Global Econamic system.
2. FPGAs have a variety of use models that differentiate them from other design elements. FPGAs can be used in the production product or can be used as a development vehicle to prove out or prototype a production design concept. When used as the production vehicle, FPGAs can be a much more flexible target than ASIC or CPU-based production vehicles. This is particularly important for a new design, one without much previous design experience. Designs with different architectural options can be easily created and tested so the optimal design is identified. FPGAs with on-chip processors (SoC FPGAs) make it also possible to trade-off CPU-based processing with hardware assisted FPGA-based acceleration functions. These advantages can dramatically reduce design, validation, testing, and failure analysis for new product developments. When used for prototyping a design, perhaps for a production ASIC, FPGA flexibility is a key benefit. An actual hardware platform, even one that doesn't run at full speed, makes it much easier to obtain detailed system performance metrics, throughput analysis data and architecture proof-of-concept results. FPGA support for hardened implementations of industry standard busses (like PCIe®, Gb Enet, XAUI, USB, CAN, and others) simplifies the testing associated with these interfaces. The newest families of FPGAs with on-chip ARM processors (SoC FPGAs), makes it easy to prototype implementations with embedded processors to. Previously developed processor code can be ported to the prototype and new code created in parallel with the hardware design effort. 3 In-Circuit FPGA Debug – Challenges and Solutions This combination of a standard processor with standard interface busses makes it possible to leverage the large ecosystem of available code libraries, drivers, functional APIs, Real Time Operating Systems, and even full Operating Systems to much more quickly create a working prototype. Additionally, once the design is solidified, the FPGA prototype can be used to capture extensive simulation test sets (for both stimulus and response) that reflect actual system data. These data sets can be invaluable in creating the final simulations for an ASIC or other production implementation. The advantages of using an FPGA as a design prototype can dramatically reduce design, validation, testing, and failure analysis for the final product implementation. In both of these common FPGA use models the flexibility of the FPGA as a design target is a key advantage. This means that many design changes and iterations would be the norm, and thus the ability to rapidly debug design errors would be critical to enabling as many design options as possible. Without an efficient debug capability much of the advantage of FPGA design flexibility will be scarified for the additional debugging time required. Luckily, FPGAs can also provide additional hardware features that dramatically simplify real-time debugging. Prior to looking at these capabilities, let’s first look at the most common types of issues an FPGA design might be faced with so we have the proper background to evaluate the efficiency and associated trade-offs of various debugging tools.
3. People using FPGAs to improve performance of systems that do things like bit-coin mining, electronic trading, and protein folding.CPU's are sequential processing devices. They break an algorithm up into a sequence of operations and execute them one at a time.FPGA's are (or, can be configured as) parallel processing devices. An entire algorithm might be executed in a single tick of the clock, or, worst case, far fewer clock ticks than it takes a sequential processor. One of the costs to the increased logic complexity is typically a lower limit at which the device can be clocked. Bearing the above in mind, FPGA's can outperform CPU's doing certain tasks because they can do the same task in less clock ticks, albeit at a lower overall clock rate. The gains that can be achieved are highly dependent on the algorithm, but at least an order of magnitude is not atypical for something like an FFT. Further, because you can build multiple parallel execution units into an FPGA, if you have a large volume of data that you want to pass through the same algorithm, you can distribute the data across the parallel execution units and obtain further orders of magnitude higher throughput than can be achieved with even a multi-core CPU.
4. As technology shrinks, critical industrial applications have to be designed with special care. VLSI circuits become more sensitive to ambient radiation: it affects to the internal structures, combinational or sequential elements. The effects, known as single event effects (SEEs), are modeled as spontaneous logical changes in a running netlist. They can be mitigated at netlist design level by means of inserting massive redundancy logic in the IC memory elements, as well as designing robust deadlock-free state machines. Current techniques for the analysis and verification of the protection logic for VLSI are inefficient and expensive, lacking either speed or analysis. This paper presents the FT- As technology shrinks, critical industrial applications have to be designed with special care. VLSI circuits become more sensitive to ambient radiation: it affects to the internal structures, combinational or sequential elements. The effects, known as single event effects (SEEs), are modeled as spontaneous logical changes in a running netlist. They can be mitigated at netlist design level by means of inserting massive redundancy logic in the IC memory elements, as well as designing robust deadlock-free state machines. Current techniques for the analysis and verification of the protection logic for VLSI are inefficient and expensive, lacking either speed or analysis. This paper presents the FT-UNSHADES system. This system is a low cost emulator focused on bit-flip insertion and SEE analysis at hardware speed, based on a Xilinx Virtex-II. Radiation tests are emulated in a highly controlled process, using a non-intrusive method. As a result the system can insert and analyse at least 80 K faults per hour in a system with 2 million test vectors.UNSHADES system. This system is a low cost emulator focused on bit-flip insertion and SEE analysis at hardware speed, based on a Xilinx Virtex-II. Radiation tests are emulated in a highly controlled process, using a non-intrusive method. As a result the system can insert and analyse at least 80 K faults per hour in a system with 2 million test vectors.
5. The Internet has fallen victim to its own stunning success. The interplay of the end-to-end design of IP and the vested interests of competing stakeholders has led to its growing ossification. Alterations to the Internet architecture that address its fundamental deficiencies or enable new services have been restricted to incremental changes. The slow pace of this process stifles innovation and the adoption of disruptive technology. A recent call to arms advances a research agenda to confront this impasse through virtualization. In addition to describing a virtual testbed for the evaluation of new network architectures, it poses a question about the long-term role of virtualization in the Internet. The architectural "purist" views virtualization as a tool for architecture evaluation and the periodic deployment of successive, singular Internet architectures. In this paper, we advance the "pluralist" view that seeks to make virtualization an architectural attribute of the Internet. By enabling a plurality of diverse network architectures to coexist on a shared physical substrate, virtualization mitigates the ossifying forces at work in the current Internet and enables continual introduction of innovative network technologies. Such a diversified Internet would allow existing architectural deficiencies to be holistically addressed as well as enable the introduction of new architectures supporting new types of applications and services. We provide a detailed exposition of the diversified Internet concept, explain how it can address the problem of network ossification and discuss some of the technical challenges that must be met to turn the vision into reality.
6. With the over-provisioned routing resource on FPGA, the topology choice for NoC implementation on FPGA is more flexible than on ASIC. However, it is well understood that the global wire routing impacts the performance of NoC on FPGA because the topology is routed by using fixed routing fabric. An important question that arises is: will the benefit of diameter reduction by using a highly connective topology outweigh the impact of global routing? To answer this question, we investigate FPGA based packet switched NoC implementations with different sizes and topologies, and quantitatively measure the impact of global routing to each of these networks. The result shows that with sufficient routing resources on modern FPGA, the global routing is not on the critical path of the system, and thus is not a dominating factor for the performance of practical multi-hop NoC system.
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