How can I fix my verilog code? Problem is in the bolded parts. Please help me de
ID: 2072511 • Letter: H
Question
How can I fix my verilog code? Problem is in the bolded parts. Please help me debug this problem and make it work correctly
// a bit full adder with carryin and carry out
module One_bit_FullAdder ( input A,
input B,
input cin,
output wire sum,
output wire carry);
// by dataflow modelling
assign sum= A ^ B ^ cin;
assign carry= (A & B) |(B & cin)|(cin & B);
endmodule
// testbench for full bit adder
module FullAdderTestBench;
reg A;
reg B;
reg cin;
wire sum;
wire carry;
One_bit_FullAdder testbench ( .A(A), .B(B),. cin(cin),.sum(sum),.carry(carry) );
initial begin
#10 A=1'b0;B=1'b0;cin=1'b0;
#10 A=1'b0;B=1'b0;cin=1'b1;
#10 A=1'b0;B=1'b1;cin=1'b0;
#10 A=1'b0;B=1'b1;cin=1'b1;
#10 A=1'b1;B=1'b0;cin=1'b0;
#10 A=1'b1;B=1'b0;cin=1'b1;
#10 A=1'b1;B=1'b1;cin=1'b0;
#10 A=1'b1;B=1'b1;cin=1'b1;
#10$stop;
end
endmodule
// 8 bit carry ripple adder module
module EightBitAdder (A, B, cin, sum, carry); // stting the conditions for the 8 bit,
input [07:0] A;
input [07:0] B;
input cin;
output [7:0]sum;
output carry;
wire[6:0] c;
// hierarchy (instantiation ) 8 bits use Inst
One_bit_FullAdder Inst1(A[0],B[0],cin,sum[0],c[0]); // takes 1 bit
One_bit_FullAdder Inst2(A[1],B[1],c[0],sum[1],c[1]); // takes 1 bit
One_bit_FullAdder Inst3(A[2],B[2],c[1],sum[2],c[2]);// takes 1 bit
One_bit_FullAdder Inst4(A[3],B[3],c[2],sum[3],c[3]);// takes 1 bit
One_bit_FullAdder Inst5(A[4],B[4],c[3],sum[4],c[4]);// takes 1 bit
One_bit_FullAdder Inst6(A[5],B[5],c[4],sum[5],c[5]);// takes 1 bit
One_bit_FullAdder Inst7(A[6],B[6],c[5],sum[6],c[6]);// takes 1 bit
One_bit_FullAdder Inst8(A[7],B[7],c[6],sum[7],carry);// takes 1 bit and carry it out
endmodule
// adder subtractor
module AddSub8Bit (X, Y, sub, result, ccn, ccz, ccv, ccc);
input [7:0] X, Y;
input sub;
output [7:0] result;
output ccn, ccz, ccv, ccc;
reg cin;
reg carry_out;
reg [7:0] X_temp, Y_temp;
reg [7:0] result_temp;
initial begin
cin=0;
carry_out=0;
end
// instantiate ripple carry adder
EightBitAdder r1( .A (X_temp),
.B (Y_temp),
.cin (cin),
.sum(result_temp), // Only net reference is allowed in this context.
.carry (carry_out) // Only net reference is allowed in this context.
);
// instiatiaion of conditional unit
condition_unit cu(.result(result_temp),
.carry_in(carry_out),
.ccn (ccn),
.ccv (ccv),
.ccz (ccz),
.ccc (ccc));
always @ (sub or X or Y)
begin
if (sub) begin // to perform subtractio invert B and cin=1
cin=1;
Y_temp=~Y;
X_temp= X;
end
else begin // to perform addition Cin=0;
cin=0;
// Y=Y;
X_temp= X;
end
end
assign result=result_temp;
endmodule
module condition_unit (result,carry_in,ccn,ccz,ccv,ccc) ;
input wire [7:0] result;
input wire carry_in;
output reg ccn;
output reg ccz ;
output reg ccv;
output reg ccc;
always @ ( result or carry_in)
begin
if (result==8'd0) begin // zero flag set
ccz=1;
end
else if (carry_in==1) begin // overflow
ccv=1;
end
else if (result[7]==1'b1) begin // sign flag set
ccn=1;
end
ccc=0;
end
endmodule
when running the code, I get these two errors
Explanation / Answer
* Corrections are Bold and italics.
module One_bit_FullAdder ( input A,
input B,
input cin,
output wire sum,
output wire carry);
// by dataflow modelling
assign sum= A ^ B ^ cin;
assign carry= (A & B) |(B & cin)|(cin & B);
endmodule
// testbench for full bit adder
module FullAdderTestBench;
reg A;
reg B;
reg cin;
wire sum;
wire carry;
One_bit_FullAdder testbench ( .A(A), .B(B),. cin(cin),.sum(sum),.carry(carry) );
initial begin
#10 A=1'b0;B=1'b0;cin=1'b0;
#10 A=1'b0;B=1'b0;cin=1'b1;
#10 A=1'b0;B=1'b1;cin=1'b0;
#10 A=1'b0;B=1'b1;cin=1'b1;
#10 A=1'b1;B=1'b0;cin=1'b0;
#10 A=1'b1;B=1'b0;cin=1'b1;
#10 A=1'b1;B=1'b1;cin=1'b0;
#10 A=1'b1;B=1'b1;cin=1'b1;
#10$stop;
end
endmodule
// 8 bit carry ripple adder module
module EightBitAdder (A, B, cin, sum, carry); // stting the conditions for the 8 bit,
input [07:0] A;
input [07:0] B;
input cin;
output [7:0]sum;
output carry;
wire[6:0] c;
// hierarchy (instantiation ) 8 bits use Inst
One_bit_FullAdder Inst1(A[0],B[0],cin,sum[0],c[0]); // takes 1 bit
One_bit_FullAdder Inst2(A[1],B[1],c[0],sum[1],c[1]); // takes 1 bit
One_bit_FullAdder Inst3(A[2],B[2],c[1],sum[2],c[2]);// takes 1 bit
One_bit_FullAdder Inst4(A[3],B[3],c[2],sum[3],c[3]);// takes 1 bit
One_bit_FullAdder Inst5(A[4],B[4],c[3],sum[4],c[4]);// takes 1 bit
One_bit_FullAdder Inst6(A[5],B[5],c[4],sum[5],c[5]);// takes 1 bit
One_bit_FullAdder Inst7(A[6],B[6],c[5],sum[6],c[6]);// takes 1 bit
One_bit_FullAdder Inst8(A[7],B[7],c[6],sum[7],carry);// takes 1 bit and carry it out
endmodule
// adder subtractor
module AddSub8Bit (X, Y, sub, result, ccn, ccz, ccv, ccc);
input [7:0] X, Y;
input sub;
output [7:0] result;
output ccn, ccz, ccv, ccc;
wire cin;
wire carry_out;
wire [7:0] X_temp, Y_temp;
wire [7:0] result_temp;
initial begin
cin=0;
carry_out=0;
end
// instantiate ripple carry adder
EightBitAdder r1( .A (X_temp),
.B (Y_temp),
.cin (cin),
.sum(result_temp), // Only net reference is allowed in this context.
.carry (carry_out) // Only net reference is allowed in this context.
);
// instiatiaion of conditional unit
condition_unit cu(.result(result_temp),
.carry_in(carry_out),
.ccn (ccn),
.ccv (ccv),
.ccz (ccz),
.ccc (ccc));
always @ (sub or X or Y)
begin
if (sub) begin // to perform subtractio invert B and cin=1
cin=1;
Y_temp=~Y;
X_temp= X;
end
else begin // to perform addition Cin=0;
cin=0;
// Y=Y;
X_temp= X;
end
end
assign result=result_temp;
endmodule
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