For this project, you will create a Model, a TestBench Model, and Simulation res

Question

For this project, you will create a Model, a TestBench Model, and Simulation results for each one of a set of Fundamental Combinational Logic Blocks. For this Assignment, you will: Create a Block Diagram with the Model primary Interface Inputs and Outputs Create a VHDL Model for each Combinational Logic block Create their corresponding Test Bench Model Simulate and Verify the expected behavior of each of the following five Combinational Logic Blocks: 4 To 2 Priority Encoder, besides the output code, an additional output indicates that the output code is Valid_H

Explanation / Answer

library ieee;
use ieee.std_logic_1164.all;

entity andGate is
port( A, B : in std_logic;
F : out std_logic);
end andGate;

architecture func of andGate is
begin
F <= A and B;
end func;

library ieee;
use ieee.std_logic_1164.all;

entity orGate is
port(   A, B : in std_logic;
F : out std_logic);
end orGate;

architecture func of orGate is
begin
F <= A or B;
end func;

library ieee;
use ieee.std_logic_1164.all;

entity notGate is
port( inPort : in std_logic;
outPort : out std_logic);
end notGate;
--
architecture func of notGate is
begin
outPort <= not inPort;
end func;

library ieee;
use ieee.std_logic_1164.all;

entity Priority_Encoder is
port( D3, D2, D1, D0 : in std_logic;
A1, A0, V : out std_logic);
end Priority_Encoder;
--
architecture Func of Priority_Encoder is

component andGate is   
port( A, B : in std_logic;
F : out std_logic);
end component;

component orGate is
port( A, B : in std_logic;
F : out std_logic);
end component;

component notGate is   
port( inPort : in std_logic;
outPort : out std_logic);
end component;

signal andOut, orOut1, orOut2, invOut: std_logic;

begin

G1: notGate port map(D2, invOut);
G2: andGate port map(invOut, D1, andOut);
G3: orGate port map(D3, D2, orOut1);
G4: orGate port map(D1, D0, orOut2);

OUT_1: orGate port map(D3, andOut, A0);   
OUT_2: orGate port map(D3, D2, A1);   
OUT_3: orGate port map(orOut1, orOut2, V);

end Func;

TEST BENCH

library ieee;
use ieee.std_logic_1164.all;

entity Priority_Encoder_tb is
end Priority_Encoder_tb;

architecture tb of Priority_Encoder_tb is

component Priority_Encoder is
port( D3, D2, D1, D0 : in std_logic;
A1, A0, V : out std_logic);
end component;

signal D3, D2, D1, D0, A1, A0, V : std_logic;

begin
mapping: Priority_Encoder
port map(D3, D2, D1, D0, A1, A0, V);

process
variable errCnt : integer := 0;
begin

D3 <= '0';
D2 <= '1';
D1 <= '0';
D0 <= '1';
wait for 15 ns;
assert(A1 = '1') report "Error 1" severity error;
assert(A0 = '0') report "Error 1" severity error;
assert(V = '1') report "Error 1" severity error;
if(A1 /= '1' or A0 /= '0' or V /= '1') then
errCnt := errCnt + 1;
end if;
  

D3 <= '1';
D2 <= '0';
D1 <= '1';
D0 <= '0';
wait for 15 ns;
assert(A1 = '1') report "Error 1" severity error;
assert(A0 = '1') report "Error 1" severity error;
assert(V = '1') report "Error 1" severity error;
if(A1 /= '1' or A0 /= '1' or V /= '1') then
errCnt := errCnt + 1;
end if;

  
D3 <= '0';
D2 <= '0';
D1 <= '0';
D0 <= '0';
wait for 15 ns;
assert(A1 = '0') report "Error 1" severity error;
assert(A0 = '0') report "Error 1" severity error;
assert(V = '0') report "Error 1" severity error;
if(A1 /= '0' or A0 /= '0' or V /= '0') then
errCnt := errCnt + 1;
end if;
  
if(errCnt = 0) then
assert false report "Success!" severity note;
else
assert false report "Faillure!" severity note;
end if;

end process;
end tb;

configuration cfg_tb of Priority_Encoder_tb is
for tb
end for;
end cfg_tb;

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