For this project, you will create a Model, a TestBench Model, and Simulation res

Question

For this project, you will create a Model, a TestBench Model, and Simulation results for each one of a set of Fundamental Combinational Logic Blocks. For this Assignment, you will: Create a Block Diagram with the Model primary Interface Inputs and Outputs Create a VHDL Model for each Combinational Logic block Create their corresponding Test Bench Model Simulate and Verify the expected behavior of each of the following five Combinational Logic Blocks: 3 To 8 Decoder 4 To 2 Priority Encoder, besides the output code, an additional output indicates that the output code is Valid_H 4 Bit To 4 Bit Comparator with A > B_H and B > A_H, and A = B_H outputs.

Explanation / Answer

3 To 8 Decoder

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity decoder3_8 is
port(
din : in STD_LOGIC_VECTOR(2 downto 0);
dout : out STD_LOGIC_VECTOR(7 downto 0)
);
end decoder3_8;

architecture decoder3_8_arc of decoder3_8 is
begin

dout <= ("10000000") when (din="000") else
("01000000") when (din="001") else
("00100000") when (din="010") else
("00010000") when (din="011") else
("00001000") when (din="100") else
("00000100") when (din="101") else
("00000010") when (din="110") else
("00000001") ;

end decoder3_8_arc;

4 to 2 Priority Encoder

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity encoder4 is
   port(
       din : in STD_LOGIC_VECTOR(3 downto 0);
       dout : out STD_LOGIC_VECTOR(1 downto 0)
   );
end encoder4;

architecture encoder4_arc of encoder4 is
begin
dout <= "00" when din="1000" else
           "01" when din="0100" else
           "10" when din="0010" else
           "11" when din="0001" else
           "ZZ";
      

end encoder4_arc;

4 Bit to 4 Bit Comparator

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity comp is
   port(
       en : in std_logic ;
       a : in STD_LOGIC_VECTOR(3 downto 0);
       b : in STD_LOGIC_VECTOR(3 downto 0);
       gt : out STD_LOGIC;
       lt : out STD_LOGIC;
       eq : out STD_LOGIC
   );
end comp;

architecture comp_arc of comp is
begin
   p0 : process (en,a,b)
   begin  
       gt <= '0';
       lt <= '0';
       eq <= '0';
       if (en='1') then
           if (a=b) then
               eq <= '1';
           elsif (a<b) then
               lt <= '1';
           else
               gt <= '1';
           end if;
       end if;
   end process;
          
     

end comp_arc;

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