An AB latch operates as follows: If A = 0 and B = 0, the latch state is Q = 0 If
ID: 1996024 • Letter: A
Question
An AB latch operates as follows: If A = 0 and B = 0, the latch state is Q = 0 If either A = 1 or B = 1 (but not both), the latch output docs not change When both A and B = 1, the latch state is Q = 1 A. Construct the state table and derive the characteristic equation for the latch. B. Design a circuit for the latch that has four two-input NAND gates and two inverters. Design a 3-bit counter using D flip-flops which counts in the following sequence: 001, 011, 010, 110, 111, 101, 100, (then repeats). Show the truth table and Karnaugh maps used in your design. A. Construct a state table and state graph for the circuit below. B. For an input sequence X = 10111, list the output values.Explanation / Answer
Show your work! You will not receive full credit for the answer alone.
1. Design a counter that counts in the sequence: 101, 100, 011, 010, 001, 000, 101, ...
Use clocked D
ip-
ops. Draw the circuit diagram. What will happen if your counter
starts in an invalid state?
A B C A+ B+ C+ Da Db Dc
000 101 101
001 000 000
010 001 001
011 010 010
100 011 011
101 100 100
110 XXX XXX
111 XXX XXX
Design Equations: Da = AC + A0B0
C
0
, Db = AC
0 + BC, Dc = C
0
If in state 110, NS is 011. If in state 111, NS is 110.
2. Repeat problem (1) using J-K
ip-
ops. You do not need to draw the circuit diagram.
A B C A+ B+ C+ Ja Ka Jb Kb Jc Kc
000 101 1X 0X 1X
001 000 0X 0X X1
010 001 0X X1 1X
011 010 0X X0 X1
100 011 X1 1X 1X
101 100 X0 0X X1
110 XXX XX XX XX
111 XXX XX XX XX
Design Equations: Ja = B0
C
0
, Ka = C
0
, Jb = AC
0
, Kb = C
0
, Jc = 1, Kc = 1
If in state 110, NS is 001. If in state 111, NS is 111. It would be wise to redesign this
state machine so state 111 leads to some valid state.3. Design a counter that counts in the sequence: 000, 010, 001, 100, 011, 110, 000, ...
Use clocked T
ip-
ops. Design your counter to go to state 000 from all invalid states.
There is no need to draw a circuit diagram.
A B C A+ B+ C+ Ta Tb Tc
000 010 010
001 100 101
010 001 011
011 110 101
100 011 111
101 000 101
110 000 110
111 000 111
Design Equations: T a = A + C, T b = C
0 + AB, T c = C + A0B + AB0
4. Do problem 14.4 on page 380 of your text.
S0 S2 S3 S6
S1 S4 S5 S7
S4: 1 & 0
0 0 0 0
0 0 0 1
1 1 1 1
1 1 1
0
0 0 0
0 0 0
0,1
S0: nothing
S5: 1 & 0 & 0
S3: 00
S2: 0
S1: 1
S6: 000
S7: 1 & 0 & 0 & 0
5. Do problem 14.7 on page 380 of your text.
See solutions in your book for a state table. A 4-state state diagram is shown below.
S0
0
1
S1
0
S3: 00 or 10 : Z = 1
1
01,10
01,10
00
00,11
00,10
00,10
11
S2
S3
01,11
11
01
S0: 00 or 11 : Z = 0
S1: 01 or 10 : Z = 0
S2: 01 or 11 : Z = 16. (Optional, 2 points) Do problem 14.13 on page 381 of your text.
S0
S1
0
0 0
S2 S3 S5: 01 : Z = 1
S5 S4
1
1 1
1
0
0
0
1
0
1
1
1
0 0
1
S0: nothing : Z = 0
S1: 0 : Z = 0
S3: nothing : Z = 1
S2: 01 : Z = 0
S4: 0 : Z = 1
7. Design the state diagram for a Mealy-style clocked sequential network that investigates
an input sequence X and will produce an output Z = 1 for any input sequences ending
in 1101 or 011. Example:
X = 0 0 1 1 0 1 1 0 1 0 1 1 0 1 0
Z = 0 0 0 1 0 1 1 0 1 0 0 1 0 1 0
S0
0/0
S2
S4
S5
S3
S1
1/0
0/0
0/0
1/1
1/0
0/0
0/0
0/0
1/1
1/0
1/0
8. A 1-block is a consecutive sequence of 1s bounded on the left by 0 or by the left
end of the sequence. Design a state table for a clocked sequential state machine that
investigates an input sequence and will produce an output Z = 1 coincident with an
input X = 0 that terminates a 1-block of even length (containing an even number of
1s). Example:
X = 1 1 0 1 1 1 0 0 1 0 0 0 1 1 0 1 1 1 1 0 1 0
Z = 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0
NS Z
PS X=0 X=1 X=0 X=1
S1 S1 S2 0 0 No 1s yet
S2 S1 S3 0 0 In a 1-block, odd # of '1's
S3 S1 S2 1 0 In a 1-block, even # of '1's9. (6 points) Design a clocked Mealy sequential network that investigates an input se-
quence X and that will produce an output Z = 1 if the total number of 1s received is
even (consider zero 1s to be an even number of 1s) and the sequence 00 has occurred
at least once. The total number of 1s received includes those received before and after
00. Example:
X = 1 0 1 0 1 0 0 1 1 0 1
Z = 0 0 0 0 0 0 0 1 0 0 1
A minimum of six states is required. Design your network using NAND gates, NOR
gates, and three J-K
ip-
ops. Assign 000 to the start state.
1/0
0/0
0/0
1/1
0/1
0/1
0/0
1/0
0/0
1/0
1/0
1/0
PS X=0 X=1 X=0
0
1
0
1
0
0
Jc = B’C’X’, Kc = A’B’X, Z = A’CX’ + ACX
X=1
0
0
0
0
0
1
NS Z
001: S1 - even # 1s, and 0
000: S0 - even # 1s, no 00
010: S2 - odd # 1s, no 00
011: S3 - even # 1s and 00
100: S4 - odd # 1s, and 0
101: S5 - odd # 1s and 00
S0
S1
S2
S3
S4
S5
S1 S2
S3 S2
S4 S0
S3 S5
S5 S0
S5 S3
S0
S2
S4
S1
S5
S3
Ja = BC’X’ + BCX, Ka = X, Jb = CX + A’X + A’C, Kb = C’ + X,
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