What are the solutions to this problem? Thanks! What are the solutions to this p

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What are the solutions to this problem? Thanks!

What are the solutions to this problem? Transistors J1, J2, and J3 are p-channel junction-FETs or JFETs. They operate similarly to MOSFETs except their gate is not separated from the channel by an insulator. The gate-source junction is a reverse-biased n-p junction (the gate is higher in potential than the source). You can consider them PMOS transistors for the purposes of understanding the circuit. JFET J3 acts as a current source in this configuration. ZD I is a zener diode and under normal operation it maintains a constant reverse-bias voltage, acting as a constant voltage source. Q13 then has a constant base voltage. The group J3, ZD I. Q13, and R11 together implement a constant current source, or the "magic IREF" The group Q9, Q10, R7 are a "2 Vb" generator to properly shift the two base voltages for the complementary emitter-follower circuit of Q11, R8, R9, and Q12. Do a KVL between the Q12, Q11 base terminals to see this property. These three parts act as a constant voltage source Identify the two current mirror groups in this circuit. For each current mirror, identify which transistor is the ref input and which transistor(s) are the corresponding mirror outputs. What is the role or purpose of Q3? Also discuss this in the context of it being part of a differential pair circuit and the importance of the left-right branches being symmetric to the circuit's ability to reject common-mode signals. In relation to the common-mode input to single-ended output gains measured in steps 1 and 4 of Lab 3 ( Av (A/cm) = ): what additional benefit does the resistor R4 provide in implementing the tail current source for the J1-J2 differential pair?. Identify the single transistor amplifier type implemented by Q5. Identify the single-transistor amplifier type implemented by Q6. Are there any cascode circuits in this schematic? All component values shown are nominal. Includes bias and trim circuitry

Explanation / Answer

1) the two current mirror gropus in this circuit are Q8+Q7 and Q8+Q4. The reference current input is in the collector of Q8 for each mirror and the transistors that are mirroring the current I(ref) are Q7 and Q4 respectively.

2) Q3 (toghether with Q1 and Q2) constitute the ACTIVE LOAD of the differential input stage (J1+J2). Thus transitors Q3 (plus Q1 and Q2) act as a MODIFIED Wilson current mirror. The role of Q3 in this modified current mirror is to transform a double ended differential output to a single ended differential output with no loss of gain or CMMR (commom mode rejection ratio).

Thus the single ended output of the active load will be in the collector of Q2. (The other output of the double ended differential load from the collector of Q1 is "closed" by the transitor Q3)

3) Resistor R4 increases the actual resistance provided by the current source Q4 (to the tail of the input differential pair J1+J2) . Thus the total amplification will decrease Av =Rc/(2*Rtail) and the CMMR (common mode rejectio ratio of the input differential pair J1+J2) will INCREASE.

4) Q5 is what is called an emitter repeater (or said in other words a common collector amplifier). It repeat the voltage in its base on the emitter resistance, provinding a very high input resistance in its base.

5) Q6 is what is called a common emitter amplifier (both input and output circuits have as common the emitter of the transitor). the input signal is between base and emitter and the output signal is between the emitter and collector . This configuration provides high amplification factors for input signals.

6) There are not any cascode circuits in this schematics. A cascode circuit would have the emitter of one trasistor connected to the collector of the other transistor and their bases driven by separate voltages.

A cascode circuit would be similar to Q6+Q10 but with the base of Q10 driven by a separate base voltage. Thus Q6+Q10 is not a cascode circuit.

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