This problem concerns the design of a circuit to find the square of a floating-p

Question

This problem concerns the design of a circuit to find the square of a floating-point number. F times 2^E. F is a normalized 5-bit fraction, and E is a 5-bit integer: negative numbers are represented in 2's complement. The result should be properly normalized. Take advantage of the fact that (-F)^2 = F^2. Draw a block diagram of the circuit. (Use only one adder and one complementer.) State your procedure, taking all special cases into account. Illustrate your procedure for F = 1.0110 E = 00100 Draw an SM chart for the main controller. You may assume that multiplication is earned out using a separate control circuit which outputs Mdone = 1 when multiplication is complete Write a VHDL description of the system.

Explanation / Answer

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;
ENTITY prob IS
PORT ( R : IN STD_LOGIC_VECTOR(23 DOWNTO O):
Clock, Resetn, L, U : IN STD_LOGIC;
Q : BUFFER STD_LOGIC_VECTOR(23 DOWNTO 0));
END prob ;
ARCHITECTURE Behavior OF prob IS
BEGIN
PROCESS (Clock, Resetn)
BEGIN
IF Resetn ‘0’ THEN
Q <= (OTHERS => ‘0’);
ELSIF Clock'EVENT AND Clock = ‘1’ THEN
IF L = ‘1’ THEN
Q <= R;
ELSIF U = ‘1' THEN
Q<=Q+1;
ELSE
Q <= Q—1;
ENDIF;
END IF ;
END PROCESS;

END Behaviour ;

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