A positive edge-triggered J-K flip-flop is used to produce a two-phase clock. Ho

Question

A positive edge-triggered J-K flip-flop is used to produce a two-phase clock. However, when the circuit is operated it produces erratic results. Close examination with a scope reveals the presence of glitches. What causes the glitches, and how might the problem be corrected?

A. The PRESET and CLEAR terminals may have been left floating; they should be properly terminated if not being used. B. The problem is caused by a race condition between the J and K inputs; an inverter should be inserted in one of the terminals to correct the problem. C. A race condition exists between the Q and Q outputs to the AND gate; the AND gate should be replaced with a NAND gate. D. A race condition exists between the clock and the outputs of the flip-flop feeding the AND gate; replace the flip-flop with a negative edge-triggered J-K Flip-Flop.

Explanation / Answer

D is correct

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